參數(shù)資料
型號(hào): MB91101APF-G-JNE1
廠商: FUJITSU LTD
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù): 69/100頁(yè)
文件大?。?/td> 2083K
代理商: MB91101APF-G-JNE1
MB91101 Series
70
DS07-16301-6E
The relation between the input waveform of source oscillation and the output waveform of CLK pin for
configured by CHC/CCK1/CCK0 settings of GCR (gear control register) is as follows:
However, in this chart source oscillation input means X0 input clock.
CCK1/0: “00”
Source oscillation input
(when using the doubler)
Source oscillation input
(1) PLL system
(CHC bit of GCR set to “0”)
(2) 2 dividing system
(CHC bit of GCR set to “1”)
(a) Gear
× 1 CLK pin
CCK1/0: “00”
(b) Gear
× 1/2 CLK pin
CCK1/0: “01”
(c) Gear
× 1/4 CLK pin
CCK1/0: “10”
(d) Gear
× 1/8 CLK pin
CCK1/0: “11”
tCYC
(a) Gear
× 1 CLK pin
tC
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