參數(shù)資料
型號: MB91101APF-G-JNE1
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù): 55/100頁
文件大?。?/td> 2083K
代理商: MB91101APF-G-JNE1
MB91101 Series
58
DS07-16301-6E
13. External Bus Interface
The external bus interface controls the interface between the device and the external memory and also the
external I/O, and has the following features.
25-bit (32 Mbytes) address output
6 independent banks owing to the chip select function.
Can be set to anywhere on the logical address space for minimum unit 64 Kbytes.
Total 32 Mbytes
× 6 area setting is available by the address pin and the chip select pin.
8/16-bit bus width setting are available for every chip select area.
Programmable automatic memory wait (Max for 7 cycles) can be inserted.
DRAM interface support
Three kinds of DRAM interface: Double CAS DRAM (normally DRAM I/F)
Single CAS DRAM
Hyper DRAM
2 banks independent control (RAS, CAS, etc. control signals)
DRAM select is available from 2CAS/1WE and 1CAS/2WE.
Hi-speed page mode supported
CBR/self refresh supported
Programmable waveform
Unused address/data pin can be used for I/O port.
Little endian mode supported
Clock doubler: Internal bus 50 MHz, external bus 25 MHz operation
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