參數(shù)資料
型號: MB91101APF-G-JNE1
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 50 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁數(shù): 15/100頁
文件大?。?/td> 2083K
代理商: MB91101APF-G-JNE1
MB91101 Series
DS07-16301-6E
21
Condition code register (CCR)
S-flag: Specifies a stack pointer used as R15.
I-flag: Controls user interrupt request enable/disable.
N-flag: Indicates sign bit when division result is assumed to be in the 2’s complement format.
Z-flag: Indicates whether or not the result of division was “0”.
V-flag: Assumes the operand used in calculation in the 2’s complement format and indicates whether or
not overflow has occurred.
C-flag: Indicates if a carry or borrow from the MSB has occurred.
System condition code register (SCR)
T-flag: Specifies whether or not to enable step trace trap.
Interrupt level mask register (ILM)
ILM4 to ILM0: Register for holding interrupt level mask value. The value held by this register is used as a
level mask. When an interrupt request issued to the CPU is higher than the level held by
ILM, the interrupt request is accepted.
ILM4
ILM3
ILM2
ILM1
ILM0
Interrupt level
High-low
00000
0
High
:
01000
15
:
11111
31
Low
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