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3.8 Standby Mode (Low Power Consumption)
Table 3.8-2 Explanation of the Functions of Each Bit of the Standby Control Register (STBC)
Bit name
Function
Bit 7
STP:
Stop bit
Bit to specify the transition to the stop mode
A transition to the stop mode is caused by writing "1" into
this bit.
Operations are not affected if "0" is written into this bit.
When this bit is read, "0" is always read.
Bit 6
SLP:
Sleep bit
Bit to specify the transition to the sleep mode
A transition to the sleep mode is caused by writing "1" into
this bit.
Operations are not affected if "0" is written into this bit.
When this bit is read, "0" is always read.
Bit 5
SPL:
Pin state designate bit
Bit to specify the external pin state in stop mode and
watch mode
If "0" is written into this bit, the external pin state (level)
when making a transition to the stop or watch mode is
retained.
If "1" is written into this bit, the external pins are put into
high impedance when making a transition to the stop or
watch mode (The pins are raised to the "H" level if "pull-
up resistor present" is selected in the pull-up setting
register).
This bit is set to "0" by a reset.
Bit 4
RST:
Software reset bit
Bit to specify the software reset
An internal reset source in four instruction cycles caused
by writing "0" into this bit.
Operations are not affected if "1" is written into this bit.
When this bit is read, "1" is always read.
[Reference:]
If the software reset is triggered in subclock mode,
operation starts in main clock mode after taking the
oscillation stabilization wait time. Thus, the reset signal is
output during oscillation stabilization wait time.
Bit 3
TMD:
Watch bit
Bit to specify the transition to the watch mode
Write operation to this bit is valid only in subclock mode
(SYCC: SCS=0).
A transition to the watch mode is caused by writing "1"
into this bit.
Operations are not affected if "0" is written into this bit.
When this bit is read, "0" is always read.
Bit 2
Bit 1
Bit 0
Unused bits
The read value is undefined.
Writing has no effect on operation.