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參數(shù)資料
| 型號： | MB86960APF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 35/66頁 |
| 文件大?。?/td> | 376K |
| 代理商： | MB86960APF-G |
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MB86960
40
RECEIVER CIRCUITS
The receiver includes a receive state machine, serial to
parallel conversion, pipe-line FIFO, preamble recogni-
tion, bit and byte framing, address filtering, CRC
and other error checking and ‘end-of-packet’ symbol
recognition.
The receiver state machine provides sequencing of events
for the receiver, including idle, busy, address filtering,
data storage, etc. It detects various receive error
conditions and sets appropriate bits within the DLC
Registers.
A small data FIFO provides elastic buffering for
synchronization with the buffer controller timing, and
buffering data while the buffer controller is servicing
other buffer memory access requests.
All received bytes are delayed by four bytes before
storing in the receive buffer so that the last four bytes
of the packet can be stripped and checked for correct
CRC. (The CRC bytes are not transferred to the
receive buffer.)
During reception, packets are automatically rejected if
space in the receive buffer is insufficient to hold the entire
received packet. Status bits in the receive status register
are set to indicate this and other errors. The receive errors
are: 1) bus read error, which occurs if the host system
attempts to read from an empty receive buffer (this need
never occur if the RX BUF EMPTY bit is checked), 2)
short packet error, 3) alignment error (incomplete byte
fragment at end of packet), 4) CRC error and 5) buffer
overflow. There is one additional possible receive error
which the chip leaves to the software to check -- length
error. When the length of the packet does not match the
value in the Length Field of an 8802–3 packet, this is a
length error. Some protocols use the length field for other
purposes, for example, the DIX protocol uses it for a
packet type code. In this case, allowed type codes do not
overlap allowed packet length values, providing a means
to distinguish which protocol is being used (if length
value >1500, it’s DIX type code). Length check can be
made conditional on protocol type if necessary to support
other protocols like DIX.
Figure 14. Encoder/Decoder Block Diagram
COLLISION
SIGNAL
DECODER
COLLISION
SIGNAL
RECEIVER
COL
INTERFACE TO
ENCODER/DECODER
AUI
INTERFACE
COL+
RXDATA+
PLL
DECODER
RX LINE
RECEIVER
COL
RCK
RXD
LOOKBACK
CRYSTAL
OSCILLATOR
X2
X1
MANCHESTER
ENCODER
TX LINE
DRIVER
TXDATA
TXDATA+
TEN
TXD
LBC
TCK
CRS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MB86961A | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:UNIVERSAL INTERFACE FOR 10BASET |
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