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| 型號： | MB86960APF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 22/66頁 |
| 文件大?。?/td> | 376K |
| 代理商： | MB86960APF-G |
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MB86960
29
Configuration Registers 0 and 1
Basic system configuration bits are found in these two
registers. Among the configuration controls found here
are physical packet buffer memory size, partitioning
between transmit and receive buffers, widths of memory
and system buses, byte lane control, chip configuration
and power down control. Most of these configuration
parameters will be programmed only during initialization
after power start and hardware reset. See Tables 12 and
13.
Table 12. DLCR6 — Configuration Register 0
BIT
SYMBOL
TYPE
DESCRIPTION
7
DLC EN
R
W
1
ENABLE DATA LINK CONTROLLER: When low, enables the receiver and transmitter
sections of the NICE chip. This bit must be set high during initialization and later set low to
enable loopback testing and operation of the network. Program NODE ID only when this bit is
high.
6
1
N
0
RESERVED: Write 1.
5
SB/SW
R
W
1
SYSTEM BYTE/WORD BUS WIDTH: When high, system bus will operate in 8-bit data
mode; when low, 16-bit data mode is selected. See also BB/BW below.
4
BB/BW
R
W
1
BUFFER BYTE/WORK WIDTH: When high, buffer memory will operate in 8-bit data
mode; when low, 16-bit data mode is selected. See table for allowable combinations with
SB/SW:
SB/SW
BB/BW
SYSTEM
BUFFER
0
word
0
1
word
byte
10
Do not use
1
byte
3, 2
TBS 1, 0
R
W
01
TRANSMIT BUFFER SIZE: Selects size of Transmit Buffer(s). See table:
00
1
2KB
01
2
2KB
4KB
10
2
4KB
8KB
11
2
8KB
16KB
TBS
No. TX
Size each
Total Size
1,0
BUFS
TX BUF
1, 0
BS1, 0
R
W
10
BUFFER SIZE: Selects physical size of total SRAM buffer memory for both transmit and
receive functions. See table:
BS1
BS0
SRAM Size
0
8KB
0
1
16KB
10
32KB
1
64KB
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相關代理商/技術參數(shù) |
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