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MAX3301E/MAX3302E
USB On-the-Go Transceivers and Charge Pumps
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Detailed Description
The USB OTG specification defines a dual-role USB
device that acts either as an A device or as a B device.
The A device supplies power on VBUS and initially
serves as the USB host. The B device serves as the ini-
tial peripheral and requires circuitry to monitor and pulse
VBUS. These initial roles can be reversed using HNP.
The MAX3301E/MAX3302E combine a low- and full-
speed USB transceiver with additional circuitry required
by a dual-role device. The MAX3301E/MAX3302E
employ flexible switching circuitry to enable the device
to act as a dedicated host or peripheral USB transceiv-
er. For example, the charge pump can be turned off and
the internal regulator can be powered from VBUS for
bus-powered peripheral applications.
The
Selector Guide shows the differences between the
MAX3301E and MAX3302E. The MAX3301E powers up
in its lowest power state and must be turned on by set-
ting the sdwn bit to 0. The MAX3302E powers up in the
operational, VP/VM USB mode. This allows a micro-
processor (P) to use the USB port for power-on boot-
up, without having to access I2C. To put the MAX3302E
into low-power shutdown, set the
sdwn bit to 0. In the
MAX3302E, special-function register 2 can be
addressed at I2C register location 10h, 11h (as well as
locations 16h, 17h) to support USB OTG serial-interface
engine (SIE) implementations that are limited to I2C
register addresses between 0h and 15h.
Transceiver
The MAX3301E/MAX3302E transceiver complies with
the USB version 2.0 specification, and operates at full-
speed (12Mbps) and low-speed (1.5Mbps) data rates.
Set the data rate with the SPD input. Set the direction of
data transfer with the
OE/INT input. Alternatively, control
transceiver operation with control register 1 (Table 7)
and special-function registers 1 and 2 (see Tables 14,
15, and 16).
Level Shifters
Internal level shifters allow the system-side interface to
run at logic-supply voltages as low as +1.65V. Interface
logic signals are referenced to the voltage applied to
the logic-supply voltage, VL.
Charge Pump
The MAX3301E/MAX3302E’s OTG-compliant charge
pump operates with +3V to +4.5V input supply voltages
(VCC) and supplies a +4.8V to +5.25V OTG-compatible
output on VBUS while sourcing the 8mA or greater out-
put current that an A device is required to supply.
Connect a 0.1F flying capacitor between C+ and C-.
Bypass VBUS to GND with a 1F to 6.5F capacitor, in
accordance with USB OTG specifications. The charge
pump can be turned off to conserve power when not
used. Control of the charge pump is set through the
vbus_drv bit (bit 5) of control register 2 (see Table 8).
Linear Regulator (TRM)
An internal 3.3V linear regulator powers the transceiver
and the internal 1.5kΩ D+/D- pullup resistor. Under the
control of internal register bits, the linear regulator can be
powered from VCC or VBUS. The regulator power-supply
settings are controlled by the reg_sel bit (bit 3) in special-
function register 2 (Tables 15 and 16). This flexibility
allows the system designer to configure the MAX3301E/
MAX3302E for virtually any USB power situation.
The output of the TRM is not a power supply. Do not use
as a power source for any external circuitry. Connect a
1.0F (or greater) ceramic or plastic capacitor from TRM
to GND, as close to the device as possible.
VBUS Level-Detection Comparators
Comparators drive interrupt source register bits 0, 1,
and 7 (Table 10) to indicate important USB OTG VBUS
voltage levels:
VBUS is valid (vbus_vld)
USB session is valid (sess_vld)
USB session has ended (sess_end)
The vbus_valid comparator sets vbus_vld to 1 if VBUS is
higher than the VBUS valid comparator threshold. The
VBUS valid status bit (vbus_vld) is used by the A device
to determine if the B device is sinking too much current
(i.e., is not supported). The session_valid comparator
sets sess_vld to 1 if VBUS is higher than the session
valid comparator threshold. This status bit indicates that
a data transfer session is valid. The session_end com-
parator sets sess_end to 1 if VBUS is higher than the
Figure 12. Comparator Network Diagram
VBUS
VBUS_VLD
VTH-VBUS
VTH-SESS_VLD
VTH-SESS_END
SESS_VLD
SESS_END