參數(shù)資料
型號: MAX3301EETJ+T
廠商: Maxim Integrated Products
文件頁數(shù): 35/38頁
文件大?。?/td> 0K
描述: IC USB TXRX OTG 32-TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 收發(fā)器
規(guī)程: USB 2.0
電源電壓: 3 V ~ 4.5 V
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-TQFN-EP(5x5)
包裝: 帶卷 (TR)
MAX3301E/MAX3302E
USB On-the-Go Transceivers and Charge Pumps
6
_______________________________________________________________________________________
I2C-/SMBus-COMPATIBLE TIMING SPECIFICATIONS
(VCC = +3V to +4.5V, VL = +1.65V to +3.6V, CFLYING = 100nF, CVBUS = 1F, ESRCVBUS = 0.1Ω (max), TA = TMIN to TMAX, unless
otherwise noted. Typical values are at VCC = +3.7V, VL = +2.5V, TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial Clock Frequency
fSCL
400
kHz
Bus-Free Time Between Stop and
Start Conditions
tBUF
1.3
s
Start-Condition Hold Time
tHD_STA
0.6
s
Stop-Condition Setup Time
tSU_STO
0.6
s
Clock Low Period
tLOW
1.3
s
Clock High Period
tHIGH
0.6
s
Data Setup Time
tSU_DAT
100
ns
Data Hold Time
tHD_DAT
(Note 4)
0.9
s
Rise Time of SDA and SCL
tR
(Note 5)
20 +
0.1 x
CB
300
ns
Fall Time of SDA and SCL
tF
Measured from 0.3 x VL to 0.7 x VL (Note 5)
300
ns
Capacitive Load for each Bus
Line
CB
400
pF
SDA AND SCL I/O STAGE CHARACTERISTICS
Input-Voltage Low
VIL
0.3 x
VL
V
Input-Voltage High
VIH
0.7 x
VL
V
SDA Output-Voltage Low
VOL
ISINK = 3mA
0.4
V
Pulse Width of Suppressed Spike
tSP
(Note 6)
50
ns
Note 2: Parameters are 100% production tested at +25
°C. Limits over temperature are guaranteed by design.
Note 3: Guaranteed by bench characterization. Limits are not production tested.
Note 4: A master device must provide a hold time of at least 300ns for the SDA signal to bridge the undefined region of SCL’s falling
edge.
Note 5: CB is the total capacitance of one bus line in pF, tested with CB = 400pF.
Note 6: Input filters on SDA, SCL, and ADD suppress noise spikes of less than 50ns.
SMBus is a trademark of Intel Corporation.
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