addressed at I2C register location 10h, 11h (as well as locations 16h, 17h) to s" />
參數(shù)資料
型號: MAX3301EETJ+T
廠商: Maxim Integrated Products
文件頁數(shù): 19/38頁
文件大小: 0K
描述: IC USB TXRX OTG 32-TQFN-EP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 收發(fā)器
規(guī)程: USB 2.0
電源電壓: 3 V ~ 4.5 V
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-TQFN-EP(5x5)
包裝: 帶卷 (TR)
addressed at I2C register location 10h, 11h (as well as
locations 16h, 17h) to support USB OTG SIE implemen-
tations that are limited to I2C register addresses
between 0h and 15h.
ID and Manufacturer Register Address Map
Table 17 provides the contents of the ID registers of the
MAX3301E/MAX3302E. Addresses 00h and 01h com-
prise the vendor ID registers. Addresses 02h and 03h
comprise the product ID registers. Addresses 14h and
15h comprise the revision ID registers.
Audio Car Kit
Many cell phones are required to interface to car kits.
Depending upon the car kit, the interface to the phone
may be required to support any or all of the following
functions:
Audio input
Audio output
Charging
Control and status
D+ and D- of the MAX3301E/MAX3302E go to a high-
impedance state when in shutdown mode, allowing
external signals (including audio) to be multiplexed onto
these lines.
External Components
External Resistors
Two external resistors (27.4Ω ±1%) are required for
USB connection. Install one resistor in series between
D+ of the MAX3301E/MAX3302E and D+ of the USB
connector. Install the other resistor in series between D-
of the MAX3301E/MAX3302E and D- of the USB con-
nector (see the
Typical Operating Circuit).
External Capacitors
Five external capacitors are recommended for proper
operation. Install all capacitors as close to the device as
possible. Decouple VL to GND with a 0.1F ceramic
capacitor. Bypass VCC to GND with a 1F ceramic
capacitor. Bypass TRM to GND with a 1F (or greater)
ceramic or plastic capacitor. Connect a 100nF flying
capacitor between C+ and C- for the charge pump (see
the
Typical Operating Circuit). Bypass VBUS to GND
with a 1F to 6.5F ceramic capacitor in accordance
with USB OTG specifications.
ESD Protection
To protect the MAX3301E/MAX3302E against ESD, D+,
D-, ID_IN, and VBUS, have extra protection against stat-
ic electricity to protect the device up to ±15kV. The ESD
structures withstand high ESD in all states; normal oper-
MAX3301E/MAX3302E
USB On-the-Go Transceivers and Charge Pumps
26
______________________________________________________________________________________
BIT NUMBER
SYMBOL
CONTENTS
VALUE AT
POWER-UP
0
vbus_vld
Set to 0 to disable the vbus_vld interrupt for a low-to-high transition. Set to 1 to
enable the vbus_vld interrupt for a low-to-high transition. See Tables 10 and 11.
0
1
sess_vld
Set to 0 to disable the sess_vld interrupt for a low-to-high transition. Set to 1 to
enable the sess_vld interrupt for a low-to-high transition. See Tables 10 and 11.
0
2
dp_hi
Set to 0 to disable the dp_hi interrupt for a low-to-high transition. Set to 1 to
enable the dp_hi interrupt for a low-to-high transition. See Tables 10 and 11.
0
3
id_gnd
Set to 0 to disable the id_gnd interrupt for a low-to-high transition. Set to 1 to
enable the id_gnd interrupt for a low-to-high transition. See Tables 10 and 11.
0
4
dm_hi
Set to 0 to disable the dm_hi interrupt for a low-to-high transition. Set to 1 to
enable the dm_hi interrupt for a low-to-high transition. See Tables 10 and 11.
0
5
id_float
Set to 0 to disable the id_float interrupt for a low-to-high transition. Set to 1 to
enable the id_float interrupt for a low-to-high transition. See Tables 10 and 11.
0
6
bdis_acon
Set to 0 to disable the bdis_acon interrupt for a low-to-high transition. Set to 1 to
enable the bdis_acon interrupt for a low-to-high transition. See Tables 10 and 11.
0
7
cr_int_sess_end
Set to 0 to disable the cr_int_sess_end interrupt for a low-to-high transition.
Set to 1 to enable the cr_int_sess_end interrupt for a low-to-high transition.
See Tables 10 and 11.
0
Table 13. Interrupt-Enable High Register (Write to Address 0Eh to Set, Write to Address
0Fh to Clear)
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