參數(shù)資料
型號(hào)： MAX3301EETJ+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 15/38頁(yè)
文件大小： 0K
描述： IC USB TXRX OTG 32-TQFN-EP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 收發(fā)器
規(guī)程： USB 2.0
電源電壓： 3 V ~ 4.5 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-TQFN-EP（5x5）
包裝： 帶卷 (TR)
MAX3301E/MAX3302E
USB On-the-Go Transceivers and Charge Pumps
22
______________________________________________________________________________________
REGISTER
MEMORY ADDRESS
DESCRIPTION
Vendor ID
00h, 01h
Read only. The contents of registers 00h and 01h are 6Ah and 0Bh, respectively.
Product ID
02h, 03h
Read only. The contents of registers 02h and 03h are 01h and 33h, respectively.
Control 1
04h (set)
05h (clear)
Sets operating modes, maximum data rate, and direction of data transfer.
Control 2
06h (set)
07h (clear)
Controls D+/D- pullup/pulldown resistor connections, ID_IN state, and VBUS
behavior.
Interrupt source
08h (read)
Read only.
Unused*
09h
Not used.
Interrupt latch
0Ah (set)
0Bh (clear)
Indicates which interrupts have occurred.
Interrupt-enable
Falling edge
0Ch (set)
0Dh (clear)
Enables interrupts for high-to-low transitions.
Interrupt-enable
Rising edge
0Eh (set)
0Fh (clear)
Enables interrupts for low-to-high transitions.
Unused*/Special
Function 2
10h (set)
11h (clear)
MAX3301E: Not used.
MAX3302E: Alternate register addresses for special-function register 2. This
register is also accessible from 16h and 17h.
Special function 1
12h (set)
13h (clear)
Enables hardware/software control of the MAX3301E's behavior, interrupt activity,
and operating modes.
Revision ID
14h, 15h
Read only. The contents of registers 14h and 15h are 77h and 41h, respectively.
Special function 2
16h (set)
17h (clear)
Sets operating modes,
INT output configuration, D+/D- behavior in audio mode,
and TRM source.
Unused*
18h–Fh
Not used.
Table 6. Register Map
Burst-Mode Read Byte Format
The MAX3301E/MAX3302E allow a master device to
read data from sequential registers with the burst-mode
read byte protocol (see Figure 21). The master device
first sends the slave address, followed by a 0. The
MAX3301E/MAX3302E then sends an acknowledge bit.
Next, the master sends the register address to the
MAX3301E/MAX3302E, which then generates another
acknowledge bit. The master then sends a stop condi-
tion to the MAX3301E/MAX3302E. Next, the master
sends a start condition, followed by the MAX3301E/
MAX3302E’s slave address, and then a 1 to indicate a
read command. The MAX3301E/MAX3302E then sends
data to the master device, one byte at a time. The mas-
ter sends an acknowledge bit to the MAX3301E/
MAX3302E after each data byte, and the register
address of the MAX3301E/MAX3302E increments after
each byte. This continues until the master sends a stop
condition. If an unsupported register address is encoun-
tered, the MAX3301E/MAX3302E send a byte of zeros.
Registers
Control Registers
There are two read/write control registers. Control regis-
ter 1 (Table 7) sets operating modes, sets the data rate,
and controls the direction of data transfer. Control regis-
ter 2 (Table 8) connects the D+/D- pullup or pulldown
resistors, sets the VBUS charge/discharge conditions,
and grounds ID_IN. The control registers have two
addresses that implement write-one-set and write-one-
clear features for each of these registers. Writing a 1 to
the set address sets that bit to 1. Writing a 1 to the clear
address resets that bit to 0. Writing a 0 to either address
has no effect on the bits.
*
When writing to an unused register, the device generates a NACK and the register index does not increment.
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