參數(shù)資料
型號(hào)： MAX1383ATP+T
廠商： Maxim Integrated Products
文件頁數(shù)： 24/25頁
文件大?。?/td> 0K
描述： IC ADC 12BIT 1.25MSPS 20-TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 12
采樣率（每秒）： 1.25M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 85.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 20-WQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 20-TQFN-EP（5x5）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
8
_______________________________________________________________________________________
MAX1377 BIPOLAR FFT
M
AX1377
toc01
ANALOG INPUT FREQUENCY (kHz)
A
M
PLITUDE
(dB)
fSAMPLE = 1.25MHz
fSCLK = 20MHz
fIN = 100kHz
SINAD = 60.052dB
SNR = 69.073dB
THD = -92.267dB
SFDR = 93.225dB
VREF = 2.048V
0
-20
-40
-60
-80
-100
-120
0
100
200
300
400
500
600
MAX1377 BIPOLAR FFT
M
AX1377
toc02
ANALOG INPUT FREQUENCY (kHz)
A
M
PLITUDE
(dB)
fSAMPLE = 1.25MHz
fSCLK = 20MHz
fIN = 250kHz
SINAD = 68.720dB
SNR = 68.769dB
THD = -88.244dB
SFDR = 91.237dB
VREF = 2.048V
0
-20
-40
-60
-80
-100
-120
0
100
200
300
400
500
600
MAX1377 BIPOLAR FFT
M
AX1377
toc03
ANALOG INPUT FREQUENCY (kHz)
A
M
PLITUDE
(dB)
fSAMPLE = 1.25MHz
fSCLK = 20MHz
fIN = 500kHz
SINAD = 68.542dB
SNR = 68.554dB
THD = -90.391dB
SFDR = 94.350dB
VREF = 2.048V
0
-20
-40
-60
-80
-100
-120
0
100
200
300
400
500
600
Typical Operating Characteristics
(VAVDD = 5V/3V, VL = 3V, fSCLK = 20MHz, TA = +25°C, unless otherwise noted.)
TIMING CHARACTERISTICS (Figures 6, 10)
VAVDD = 4.25V to 5.25V, VL = 1.8V to AVDD, VREF = 4.096V, fSCLK = 20MHz for MAX1379, 50% duty cycle, CL = 30pF, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Clock Period
tCP
50
ns
SCLK Duty Cycle
tCH/tCL
45
55
%
SCLK Pulse-Width High
tCH
22.5
ns
SCLK Pulse-Width Low
tCL
22.5
ns
CL = 30pF, VL = 5V
14
CL = 30pF, VL = 3V
17
SCLK Rise to DOUT_ Transition
tDOUT
CL = 30pF, VL = 1.8V
24
ns
DOUT_ Remains Valid After
SCLK
tDHOLD
4ns
CNVST Fall to SCLK Fall
tSETUP
CL = 30pF
10
ns
CNVST Pulse Width
tCSW
20
ns
Power-Up Time; Full Power-Down
tPWR-UP
External load on REF < 3F
2
ms
SEL to CNVST Fall
tSEL_SETUP
100
120
ns
SEL Hold to CNVST Fall
10
ns
CS Fall To CNVST Fall
tCST
External load on REF < 3F
2
ms
Restart Time; Partial Power-Down
tRCV
No external load
16
Cycles
Note 1: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and the offset
error have been nulled.
Note 2: Offset nulled.
Note 3: Conversion time is defined as the number of clock cycles (16) multiplied by the clock period. Clock has 50% duty cycle.
Note 4: At sample rates below 10ksps, the input full linear bandwidth is reduced to 5kHz.
Note 5: SCLK and CNVST not switching during measurement.
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