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參數(shù)資料
| 型號： | MAX1383ATP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 19/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 1.25MSPS 20-TQFN |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 85.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WQFN 裸露焊盤 |
| 供應商設備封裝： | 20-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極 |
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS—MAX1377 (continued)
(VAVDD = 2.7V to 3.6V, VL = 1.8V to AVDD, fSCLK = 20MHz (50% duty cycle), VREF = 2.048V, REFSEL = VL, S/D = DGND, CREF =
1F; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Track-and-Hold Acquisition Time
tACQ
125
ns
Aperture Delay
2ns
Aperture-Delay Matching
2ns
Aperture Jitter
(Note 5)
30
ps
External Clock Frequency
fSCLK
20
MHz
ANALOG INPUTS (AIN1A, AIN1B, AIN2A, AIN2B)
Input Range
U/B = 0, VAIN_A - RGND
0
VREF
V
Differential Input Range
U/B = 1, VAIN_A - VAIN_B
-VREF/2
+VREF/2
V
Absolute Voltage Range
0
AVDD
V
DC Leakage Current
±1
A
Input Impedance
34
k
Input Capacitance
At each analog input
16
pF
EXTERNAL REFERENCE (REFSEL = 1)
Absolute Input Voltage Range
VREF
1.0
AVDD
+ 0.05
V
Input Capacitance
50
pF
DC Leakage Current
±1
A
Input Current
Time averaged at maximum throughput rate
800
A
INTERNAL REFERENCE (REFSEL = 0)
Reference Voltage Level
2.028
2.048
2.068
V
ISOURCE = 0 to 1mA
1
Load Regulation
ISINK = 0 to 50A
1
mV/mA
Voltage Temperature Coefficient
±50.0
ppm/
oC
DIGITAL INPUTS (SCLK, CNVST,
U/B, S/D, SEL, REFSEL)
Input-Voltage Low
VIL
0.3 x
VL
V
Input-Voltage High
VIH
0.7 x
VL
V
Input Leakage Current
IIL
±10
A
DIGITAL OUTPUT (DOUT1, DOUT2)
Output Load Capacitance
CDOUT
For stated timing performance
30
pF
Output-Voltage Low
VOL
ISINK = 5mA
0.4
V
Output-Voltage High
VOH
ISOURCE = 1mA, VL
≥ 2.7V
VL
- 0.5V
V
Output Leakage Current
IOL
High-impedance mode (Figure 9)
±0.2
A
POWER REQUIREMENTS
Analog Supply Voltage
AVDD
2.7
3.0
3.6
V
Digital Supply Voltage
VL
1.8
AVDD
V
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