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參數(shù)資料
| 型號： | MAX1383ATP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 1.25MSPS 20-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 85.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極 |
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
18
______________________________________________________________________________________
DOUT1 (and DOUT2, if S/D = low) transitions from high
impedance to being actively driven low once the ADC
enters hold mode. DOUT_ remains low for the first three
SCLK pulses and begins outputting the conversion result
after the 4th rising edge of SCLK, MSB first. DOUT_ tran-
sitions complete tDOUT after each SCLK rising edge and
the DOUT_ values remain valid for tHOLD after the next
rising edge of SCLK. A total of 16 SCLK pulses are
required to complete a normal conversion in dual-output
mode and 28 SCLK pulses in single-output mode.
DOUT_ goes low after the 16th rising edge of SCLK and
goes high-impedance when CNVST goes high.
For continuous operation in single-output mode, pull
CNVST high after the 14th rising and before the 28th
rising edge of SCLK. In dual-output mode, if CNVST
returns high after the 14th rising and before the 16th
falling edge of SCLK, DOUT_ remains active so continu-
ous conversions can be sustained. If CNVST is low
during the 16th edge of SCLK (dual-conversion mode)
and the 28th falling edge of SCLK (single-output mode),
DOUT_ returns to its high-impedance state on the next
rising edge of CNVST or SCLK, enabling the serial inter-
face to be shared by multiple devices. See Figures 9
and 10 for single and continuous conversion timing
diagrams.
CNVST
SCLK
DOUT_
D11
D10
D9
D8
D7
D6
D5
D4
0
SINGLE CONVERSION
1
D3
D2
D1
D0
16
9
8
HIGH-Z
SCLK
DOUT_
D11
D10
D9
D8
D7
D6
D5
D4
0
1
D3
D2
D1
D0
16
14
9
8
1
CNVST
CONTINUOUS CONVERSION
CONTINUOUS-CONVERSION
SELECTION WINDOW*
*CNVST MUST GO HIGH BETWEEN THE 14TH RISING AND 16TH FALLING EDGES OF SCLK.
TO MAINTAIN CONTINUOUS CONVERSIONS, DOUT_ REMAINS LOW BETWEEN
CONVERSION RESULTS IN CONTINUOUS-CONVERSION DUAL-OUTPUT MODE.
HIGH-Z
Figure 9. Dual-Output Mode, Single and Continuous Conversions
CNVST
SCLK
1
2
3
4
14
POWER-DOWN
CONTINUOUS MODE
DOUT_ HI-Z
15
16
17
CS
Figure 8. Dual-Output CNVST Transition Modes
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