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參數(shù)資料
| 型號： | MAX1383ATP+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 13/25頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 1.25MSPS 20-TQFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1.25M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 85.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-TQFN-EP（5x5） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極；1 個差分，單極；1 個差分，雙極 |
MAX1377/MAX1379/MAX1383
Dual, 12-Bit, 1.25Msps Simultaneous-Sampling
ADCs with Serial Interface
20
______________________________________________________________________________________
Exiting Partial and Full Power-Down Modes
Drive CNVST low and allow at least 14 SCLK cycles to
elapse before driving CNVST high to exit partial or full
power-down mode. When exiting partial power-down
mode, conversions can begin immediately without hav-
ing to wait for the reference to wake-up. When exiting
full power-down mode, allow at least 2ms recovery time
after exiting to ensure that the internal reference has
settled.
In partial or full power-down mode, maintain idle SCLK
low or high to minimize power.
Applications Information
SPI and MICROWIRE
The MAX1377/MAX1379/MAX1383 are compatible with
all four modes programmed with the CPHA and CPOL
bits in the SPI or MICROWIRE control register.
Conversion begins with a CNVST falling edge. DOUT_
goes low, indicating a conversion is in progress. Two
consecutive 8-bit reads are required to get the full 12
bits from the ADC. DOUT_ transitions on the rising edge
of SCLK. DOUT_ is guaranteed to be valid tDOUT after
the rising edge of SCLK and remains valid until tDHOLD
after the next SCLK rising edge (see Figure 13).
1ST SCLK RISING EDGE
0
D11
D10
D8
D7
DOUT_
MODE
SCLK
CNVST
0
FPD
PPD
NORMAL
0
DOUT_ ENTERS THREE-STATE ONCE CNVST GOES HIGH
EXECUTE PARTIAL POWER-DOWN SEQUENCE TWICE
0
D9
0
REF
ENABLED
DISABLED
Figure 12. Full Power-Down Mode Timing Sequence
DOUT_
MODE
SCLK
CNVST
DOUT_ GOES HIGH IMPEDANCE ONCE CNVST GOES HIGH
CNVST MUST GO HIGH AFTER THE 3RD
BUT BEFORE THE 14TH
SCLK RISING EDGE
1ST SCLK RISING EDGE
PARTIAL POWER-DOWN
0
D11
D10
D9
D8
D7
NORMAL
0
REF
ENABLED
1
39
14
PPD WINDOW
Figure 11. Partial Power-Down Timing Sequence
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