參數(shù)資料
型號： MAX1329BETL+
廠商： Maxim Integrated Products
文件頁數(shù)： 57/78頁
文件大?。?/td> 0K
描述： IC DAS 12BIT 300KSPS 40-TQFN-EP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 50
系列： *
MAX1329/MAX1330
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
60
______________________________________________________________________________________
Status Register
The Status register is a 24-bit register that contains
Status bits from all blocks. Setting a Status bit causes
the interrupt output to assert when the corresponding
Interrupt Mask bit in the Interrupt Mask register is
cleared. If a Status bit is set and an event occurs to set
it again, the Status bit and interrupt output remain
asserted. All Status bits clear once the Status register
has been read successfully. Updating of the Status reg-
ister is delayed during a read until the Status register
read has been completed.
VM1A: 1.8V DVDD Voltage-Monitor Status bit (default =
0). VM1A indicates the status of the 1.8V DVDD voltage
monitor. The VM1A = 1 when the DVDD voltage drops
below the 1.8V threshold. The VM1A bit clears to 0
when the Status register is read and only if the condi-
tion is no longer true. When the 1.8V DVDD voltage
monitor is powered down, the previous state of the bit is
maintained until it is read and it cannot be set to 1 in
this state.
Note: The default state is 0. However, at power-up, the
voltage monitor asserts VM1A. Read the Status register
after power-up to reset VM1A to 0.
VM1B: 2.7V DVDD Voltage-Monitor Status bit (default =
0). VM1B indicates the status of the 2.7V DVDD voltage
monitor. VM1B = 1 when the DVDD voltage drops below
the 2.7V threshold. The VM1B bit clears to 0 when the
Status register is read and only if the condition is no
longer true. When the 2.7V DVDD voltage monitor is pow-
ered down, the previous state of the bit is maintained
until it is read and it cannot be set to 1 in this state.
Note: The default state is 0. However, at power-up, the
voltage monitor asserts VM1B. Read the Status register
after power-up to reset VM1B to 0.
VM2: AVDD Voltage-Monitor Status bit (default = 0).
VM2 indicates the status of the AVDD voltage monitor.
VM2 = 1 when the AVDD voltage drops below the
threshold programmed by the VM2CP<2:0> bits. VM2
clears to 0 when the Status register is read and only if
the condition is no longer true. When the AVDD voltage
monitor is powered down, the previous state of the bit is
maintained until it is read and it cannot be set to 1 in
this state.
ADD: ADC Done Status bit (default = 0). The ADD bit
indicates when an ADC conversion has completed and
the data is ready to be read from the ADC Data regis-
ter. ADD is set to 1 after the data from an ADC conver-
sion has been written to the ADC Data register. ADD
clears to 0 when the Status register or the ADC Data
register is read.
AFF: ADC FIFO Full Status bit (default = 0). The AFF bit
indicates that the ADC has written data to the ADC
FIFO address programmed by the AFFI<3:0> bits. The
AFF bit is set to 1 when the address has been written.
AFF clears to 0 when the Status register is read or when
the ADC FIFO register is read (any number of ADC data
words) or written.
ACF: ADC Accumulator Full Status bit (default = 0). The
ACF bit indicates that the programmed number of ADC
conversion results have been accumulated. The result
is saved in the ACCDATA<19:0> bits in the ADC
Accumulator register for the next programmed number
of accumulations before it is overwritten. The ACF bit
sets to 1 when the ADC Accumulator is filled to the pro-
grammed address. The ACF bit clears to 0 when the
Status register is read or when the ADC Accumulator
register is read or written.
Table 31. DPIO_ Mode Bit Configuration (continued)
MODE
DP_MD3
DP_MD2
DP_MD1
DP_MD0
MAX1329
MAX1330
DESCRIPTION
1
0
1
SPDT2
Digital input. SPDT2 controls the SPDT2 switch. See the Switch
Control Register section.
1
0
DRDY
Digital output. DRDY goes high when a conversion is complete
and valid ADC data is available in the ADC Data register. If the
ADC Data or Status register is read, DRDY returns low. If high,
DRDY pulses low for one ADC master clock cycle while
updating the ADC Data register before returning high.
1
GPO
Digital output. Write to the DP_LL register bits to set the GPO
level.
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參數(shù)描述
MAX1329BETL+ 功能描述:ADC / DAC多通道 12-Bit 2Ch 300ksps 5.4V Precision ADC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX1329BETL+T 功能描述:ADC / DAC多通道 12-Bit 2Ch 300ksps 5.4V Precision ADC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX132C/D 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX132CNG 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX132CNG+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit .1ksps .545V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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