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| 型號： | MAX1329BETL+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 49/78頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS 12BIT 300KSPS 40-TQFN-EP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 50 |
| 系列： | * |
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MAX1329/MAX1330
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
______________________________________________________________________________________
53
CP/VM Control Register
The CP/VM (Charge Pump/Voltage Monitor) Control
register configures the interrupt polarity, charge-pump
output voltage settings and power-down, supply volt-
age bypass switch state, and the voltage monitor set-
tings for DVDD and AVDD.
INTP: Interrupt Polarity bit (default = 0). INTP controls
the output polarity for
RST1 and RST2 when configured
as interrupt outputs. INTP = 0 results in active-low oper-
ation and INTP = 1 selects active-high operation.
VM1<1:0>: Voltage Monitor 1 (VM1) Control bits
(default = 00). VM1 monitors the voltage on DVDD. The
VM1<1:0> bits control the threshold and output settings
of VM1 (see Table 21).
RST1 and RST2 are open-drain
outputs when configured as voltage monitor outputs
and are push-pull when configured as interrupt outputs.
The VM1A status bit is set when DVDD drops below the
1.8V threshold and the VM1B status bit is set when
DVDD drops below the 2.7V threshold.
VM2CP<2:0>: Voltage Monitor 2 (VM2) and Charge-
Pump Control bits (default = 000). VM2CP<2:0> control
the charge pump, the bypass switch, and the AVDD volt-
age monitor. The charge pump generates a regulated
AVDD supply voltage from a DVDD input. When activated
(VM2CP = 100), the bypass switch internally shorts
DVDD to AVDD. VM2 monitors the voltage on AVDD and
sets the VM2 Status bit when AVDD drops below
the threshold.
CPDIV<1:0>: Charge-Pump Clock Divider bits (default =
00). The CPDIV<1:0> bits set the divider value for the
input clock to the charge pump (see Table 23). If OSCE
= 1, the input to the charge-pump clock divider is the
3.6864MHz oscillator output. If OSCE = 0 and
CLKIO<1:0> ≠ 00, the output of the CLKIO input divider
is applied to the input of the charge-pump clock divider.
The charge pump is optimized to operate with a clock
rate between 39kHz and 78kHz. Set the CPDIV<1:0>
and CLKIO<1:0> bits to provide the optimal clock
frequency for the charge pump.
Table 21. Voltage Monitor 1 Control Bit Configuration
VM11
VM10
RST1 OUTPUT
RST2 OUTPUT
VM1A STATE
(1.8V MONITOR)
VM1B STATE
(2.7V MONITOR)
0
1.8V monitor
2.7V monitor
On
0
1
1.8V monitor
Interrupt
On
Off
1
0
Interrupt
2.7V monitor
Off
On
1
Interrupt
Off
Table 20. ADC Acquisition Clock Bit
Configuration
ADC ACQUISITION CLOCKS
ACQCK1
ACQCK0
GAIN = 1, 2
GAIN = 4, 8
00
2
4
01
4
8
10
8
16
1
16
32
MSB
LSB
NAME
INTP
VM11
VM10
VM2CP2
VM2CP1
VM2CP0
CPDIV1
CPDIV0
DEFAULT
00
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1329BETL+ | 功能描述:ADC / DAC多通道 12-Bit 2Ch 300ksps 5.4V Precision ADC RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX1329BETL+T | 功能描述:ADC / DAC多通道 12-Bit 2Ch 300ksps 5.4V Precision ADC RoHS:否 制造商:Texas Instruments 轉換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40 |
| MAX132C/D | 功能描述:模數(shù)轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX132CNG | 功能描述:模數(shù)轉換器 - ADC Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX132CNG+ | 功能描述:模數(shù)轉換器 - ADC 18-Bit .1ksps .545V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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