參數(shù)資料
型號： MAX1329BETL+
廠商： Maxim Integrated Products
文件頁數(shù)： 19/78頁
文件大小： 0K
描述： IC DAS 12BIT 300KSPS 40-TQFN-EP
產(chǎn)品培訓模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝： 50
系列： *
MAX1329/MAX1330
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
26
______________________________________________________________________________________
Upon a power-on reset, the charge pump is disabled.
Enable the charge pump through the CP/VM Control
register. When the charge pump is in its off state, AVDD
is isolated from DVDD unless the bypass switch is
enabled. To bypass the charge pump and directly con-
nect DVDD to AVDD, enable (close) the bypass switch
through the CP/VM Control register (see Tables 21 and
22). During the on mode, the charge pump boosts
DVDD and regulates the voltage to generate the select-
ed output voltage at AVDD. The charge-pump output
voltage selections are 3.0V, 4.0V, or 5.0V.
The charge-pump clock and ADC clock are synchro-
nized from the same master clock. The charge pump
uses a pulse-width-modulation (PWM) scheme to regu-
late the output voltage. The charge pump supports a
maximum load of 25mA of current to an external device
including what is required for internal circuitry.
Power Modes
Three power modes are available for the MAX1329/
MAX1330: shutdown, sleep, and normal operation. In shut-
down mode, all functional blocks are powered down except
the serial interface, data registers, and wake-up circuitry (if
enabled). Sleep mode is identical to shutdown mode
except the DVDD voltage monitors (if enabled) remain
active. Global sleep or shutdown mode is initiated through a
DPIO configured as
SLP or SHDN inputs. In normal mode,
each analog and digital block can be powered up or shut
down individually through its respective control register.
Voltage Supervisors
The MAX1329/MAX1330 provide two programmable volt-
age supervisors, one for DVDD and one for AVDD. The
DVDD voltage supervisor has two thresholds (set to 1.8V
and 2.7V by default) that are both enabled after a power-
on reset. On initial power-up,
RST1 is assigned the 1.8V
monitor output and
RST2 is assigned the 2.7V monitor
output, both for DVDD. If DVDD falls below the 1.8V or
2.7V threshold, the VM1A bit or VM1B bit, respectively, in
the Status register is set. The VM1A and VM1B status
bits can also be mapped to the interrupt generator.
The default states of
RST1 and RST2 are open-drain
outputs but can be programmed as push-pull Status
register interrupts through the CP/VM Control register.
The AVDD voltage supervisor provides three program-
mable thresholds. If AVDD falls below the programmed
threshold, the VM2 bit is set in the Status register. The
VM2 status bit can also be mapped to the interrupt
generator.
Interrupt Generator
The interrupt generator accepts inputs from other internal
circuits to provide an interrupt to an external microcontroller
(C). The sources for generating an interrupt are program-
mable through the serial interface. Possible sources
include a rising or falling edge on the digital and analog
programmable inputs, ADC alarms, an ADC conversion
complete, an ADC FIFO full, an ADC accumulator full, and
the voltage-supervisor outputs. The interrupt causes
RST1
and/or
RST2 to assert when configured as an interrupt out-
put. The interrupt remains asserted until the Status register
is read. See the CP/VM Control register for programming
the
RST1 and RST2 outputs as interrupts and the Interrupt
Mask register for programming the interrupt sources.
Internal Oscillator and Programmable
Clock Dividers
The MAX1329/MAX1330 feature an internal oscillator,
which operates at a fixed frequency of 3.6864MHz. When
enabled, the internal oscillator provides the master clock
source for the ADC and charge pump. To allow external
devices to use the internally generated clock, configure
CLKIO as an output through the Clock Control register.
The CLKIO output frequency is configurable for
0.9216MHz, 1.8432MHz, and 3.6864MHz. When the inter-
nal oscillator is enabled, and regardless of the CLKIO out-
put frequency, the ADC and charge-pump clock dividers
always receive a 3.6864MHz clock signal (see Figure 3).
After a power-on reset, CLKIO defaults to an output with
the divider set to 2 (resulting in 1.8432MHz).
INTERNAL
OSCILLATOR
4.9152MHz
(OFF, ON)
CLOCK INPUT
DIVIDER
(OFF, /1, /2, /4)
OSCE = 0
CLOCK OUTPUT
DIVIDER
(OFF, /1, /2, /4)
OSCE = 1
CHARGE-PUMP
CLOCK DIVIDER
(/32, /64, /128, /256)
ADC
(ACQUIRE CLKS)
(ADC CONTROL)
(ADC SETUP)
CLKIO
SCLK
MUX
OSCE
0
1
MUX
CHARGE PUMP
(OFF, 3V, 4V, 5V)
ADC CLOCK
DIVIDER
(/1, /2, /4, /8)
Figure 3. Clock-Divider Block Diagram
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MAX1329BETL+ 功能描述:ADC / DAC多通道 12-Bit 2Ch 300ksps 5.4V Precision ADC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX1329BETL+T 功能描述:ADC / DAC多通道 12-Bit 2Ch 300ksps 5.4V Precision ADC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX132C/D 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX132CNG 功能描述:模數(shù)轉(zhuǎn)換器 - ADC Integrated Circuits (ICs) RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX132CNG+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit .1ksps .545V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32
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