參數(shù)資料
型號: MAS281
廠商: Dynex Semiconductor Ltd.
英文描述: MIL-STD-1750A Microprocessor
中文描述: 符合MIL - STD - 1750A微處理器
文件頁數(shù): 23/55頁
文件大?。?/td> 551K
代理商: MAS281
MAS281
23/55
Operation
Op Code/Ext
Mnemonic
Format
Cycles *
M
LOGICAL
Inclusive Logical OR
E1
3X
4X F
E0
4A 8
ORR
ORB
ORBX
OR
ORIM
R
B
BX
D, DX
IM
1
2
2
3
2
0
1
1
0
0
0
0
0
0
0
Logical AND
E3
3X
4X E
E2
4A 7
ANDR
ANDB
ANDX
AND
ANDM
R
B
BX
D, DX
IM
1
2
2
3
2
0
1
1
0
0
0
0
0
0
0
Exclusive Logical OR
E5
E4
4A 9
XORR
XOR
XORM
R
D, DX
IM
1
3
2
0
0
0
0
0
0
Logical NAND
E7
E6
4A B
NR
N
NIM
R
D, DX
IM
1
3
2
1
1
1
0
0
0
Set Bit
51
50
52
SBR
SB
SBI
R
D, DX
I, IX
1
4
5
0
1
2
0
0
0
Reset Bit
54
53
55
RBR
RB
RBI
R
D, DX
I ,IX
1
4
5
1
1
2
0
0
0
Test Bit
57
56
58
TBR
TB
TBI
R
D, DX
I, IX
1
3
4
0
0
1
0
0
0
Test and Set Bit
59
TSB
D,DX
4
0
2
Set Variable Bit in Register
5A
SVBR
R
1
0
1
Reset Variable Bit in Register
5C
RVBR
R
1
1
1
Test Variable Bit in Register
5E
TVBR
R
1
0
1
Store Register Through Mask
97
SRM
D,DX
4
3
0
BYTE
Load From Upper Byte
8B
8D
8C
8E
9B
9D
9C
9E
EC
LUB
LUBI
LLB
LLBI
STUB
SUB I
STLB
SLBI
XBR
D,DX
I,IX
D DX
I, IX
D,DX
I, IX
D,DX
I,IX
S
3
4
3
4
4
5
4
5
1
0
1
1
2
1
3
1
2
0
0
0
0
0
0
0
0
0
1
Load From Lower Byte
Store Into Upper Byte
Store Into Lower Byte
Exchange Bytes in Register
*
M = memory, P = processor (5 OSC cycles), B = processor (6 OSC cycles).
Table 7a: Instruction Summary (continued)
P
B
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