參數(shù)資料
型號(hào)： MAS281
廠商： Dynex Semiconductor Ltd.
英文描述： MIL-STD-1750A Microprocessor
中文描述： 符合MIL - STD - 1750A微處理器
文件頁(yè)數(shù)： 1/55頁(yè)
文件大小： 551K
代理商： MAS281
1/55
The MAS281 Microprocessor is a MIL-STD-1750A (Notice
1), 16-bit Central Processing Unit (CPU). It consists of three
CMOS/SOS large-scale integration (LSI) chips: the MA17501
Execution Unit (EU), the MA17502 Control Unit (CU), and the
MA17503 Interrupt Unit (IU). These three units can be
mounted on, and interconnected within a 64-pin ceramic
substrate. The microprocessor is also available as a 3-chip set
without the ceramic substrate (see ordering information on
page 55).
The MAS281 is optimised for real-time l/O and arithmetic
intensive operations. Key performance-enhancing features
include a parallel multiplier/accumulator, 32-bit barrel shifter,
instruction pre-fetch queue, and multiport register file.
Additional features include a comprehensive Built-ln-Test
(BIT), interval timers A and B, trigger-go counter, and Start-Up
ROM interface.
In accordance with MIL-STD-1750A, the MAS281
supports a 64K-word address space. An optional BMA31751
Memory Management Unit/Block Protect Unit (MMU(BPU))
chip may be added externally to expand this address space to
1M-words or add a 1K-word memory block protection
capability,
The MAS281 is offered in several screening grades which
are described in this document. For availability of speed
grades, please contact Dynex Semiconductor.
BLOCK DIAGRAM
FEATURES
I
MIL-STD-1750A 16-Bit Microprocessor
I
Full Performance over Military Temperature Range
(-55
°
C to + 125
°
C)
I
Radiation Hard CMOS/SOS Technology
I
Performance Optimised Architecture
- Parallel Multiplier/Accumulator
- 32-bit Barrel Shifter
- Instruction Pre-Fetch
- Multi-Port Register File
I
Implements MlL-STD-1750AOptions
- Timers A and B
- Trigger-Go Counter
- Start-Up ROM Interface
I
64 K-word Address Space Expandable to 1 M-word with
Optional MMU
MAS281
MIL-STD-1750A Microprocessor
Replaces June 1999 version, DS3563-4.0
DS3563-5.0 January 2000
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