參數(shù)資料
型號: M7A3PE600-FFG256I
元件分類: FPGA
英文描述: FPGA, 600000 GATES, PBGA256
封裝: 1 MM PITCH, FBGA-256
文件頁數(shù): 163/168頁
文件大小: 1335K
代理商: M7A3PE600-FFG256I
ProASIC3E Flash Family FPGAs
3- 26
Advanced v0.5
2.5 V LVCMOS
Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 2.5 V
applications. It uses a 5-V-tolerant input buffer and push-pull output buffer.
Table 3-29 Minimum and Maximum DC Input and Output Levels
2.5 V
LVCMOS
VIL
VIH
VOL
VOH
IOL
IOH
IOSL
IOSH
IIL
IIH
Drive
Strength
Min, V Max, V Min, V Max, V Max, V Min, V
mA
Max, mA1 Max, mA1
A2
4 mA
–0.3
0.7
1.7
3.6
0.7
1.7
4
18
16
10
8 mA
–0.3
0.7
1.7
3.6
0.7
1.7
8
37
32
10
12 mA
–0.3
0.7
1.7
3.6
0.7
1.7
12
74
65
10
16 mA
–0.3
0.7
1.7
3.6
0.7
1.7
16
87
83
10
24 mA
–0.3
0.7
1.7
3.6
0.7
1.7
24
124
169
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
Figure 3-7
AC Loading
Table 3-30 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (Typ) (V)
CLOAD (pF)
02.5
1.2
35
Note: *Measuring point = Vtrip. See Table 3-15 on page 3-17 for a complete table of trip points.
Test Point
Enable Path
Datapath
R to V
for t /t /t
CCI
LZ ZL
ZLS
35 pF for t
/t
/t /t
ZH ZHS
ZLS
ZL
5 pF for t
/t
HZ
LZ
R to GND for t
/t
HZ
ZH
ZHS
35 pF
R = 1 k
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