參數(shù)資料
型號： M7A3PE600-FFG256I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA256
封裝： 1 MM PITCH, FBGA-256
文件頁數(shù)： 109/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFG256I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
2-33
I/O Registers
Each I/O module contains several input, output, and enable registers. Refer to Figure 2-23 for a simplified
representation of the I/O block.
The number of input registers is selected by a set of switches (not shown in Figure 2-23) between registers to
implement single or differential data transmission to and from the FPGA core. The Designer software sets these
switches for the user.
A common CLR/PRE signal is employed by all I/O registers when I/O register combining is used. Input Register 2 does
not have a CLR/PRE pin, as this register is used for DDR implementation. The I/O registers combining must satisfy some
rules. For more information, refer to the ProASIC3/E I/O Usage Guide.
Note: ProASIC3E I/Os have registers to support DDR functionality (see the "Double Data Rate (DDR) Support" section on page 2-34 for
more information).
Figure 2-23 I/O Block Logical Representation
Input
Register
E = Enable Pin
A
Y
PAD
1
2
3
4
5
6
OCE
ICE
Input
Register
Input
Register
CLR/PRE
Pull-Up/Down
Resistor Control
Signal Drive Strength
and Slew-Rate Control
Output
Register
Output
Register
To FPGA Core
From FPGA Core
Output
Enable
Register
OCE
I/O / CLR or I/O / PRE / OCE
I/O / Q0
I/O / Q1
I/O / ICLK
I/O / D0
I/O / D1 / ICE
I/O / OCLK
I/O / OE
相關PDF資料
PDF描述
M7A3PE600-FFG484I FPGA, 600000 GATES, PBGA484
M7A3PE600-FFGG256I FPGA, 600000 GATES, PBGA256
M7A3PE600-FFGG484I FPGA, 600000 GATES, PBGA484
M7A3PE600-FPQ208I FPGA, 600000 GATES, PQFP208
M7A3PE600-FPQG208I FPGA, 600000 GATES, PQFP208
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