參數(shù)資料
型號(hào)： M7A3PE600-FFG484I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA484
封裝： 1 MM PITCH, FBGA-484
文件頁(yè)數(shù)： 1/168頁(yè)
文件大?。?/td> 1335K
代理商： M7A3PE600-FFG484I
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April 2006
i
2006 Actel Corporation
See the Actel website for the latest version of the datasheet.
ProASIC3E Flash Family FPGAs
with Optional Soft ARM Support
Features and Benefits
High Capacity
600 k to 3 Million System Gates
108 k to 504 kbits of True Dual-Port SRAM
Up to 616 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS
Process
Live At Power-Up (LAPU) Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
On-Chip User Nonvolatile Memory
1 kbit of FlashROM with Synchronous Interfacing
High Performance
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard
(AES)
Decryption
via
JTAG
(IEEE1532-
compliant)
FlashLock to Secure FPGA Contents
Low Power
1.5 V Core Voltage for Low Power
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-Speed, Very-Long-Line Network
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
Pro (Professional) I/O
700 Mbps DDR, LVDS-Capable I/Os
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages – Up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V/
2.5 V/1.8 V/1.5 V, 3.3 V PCI/ 3.3 V PCI-X, and LVCMOS
2.5 V/5.0 V Input
Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS
Voltage-Referenced
I/O
Standards:
GTL+ 2.5 V/3.3 V,
GTL 2.5 V/3.3 V, HSTL Class I and II, SSTL2 Class I and II,
SSTL3 Class I and II
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay
Schmitt-Trigger Option on Single-Ended Inputs
Weak Pull-Up/Down
IEEE1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages Across the ProASIC3E Family
Clock Conditioning Circuit (CCC) and PLL
Six CCC Blocks, Each with an Integrated PLL
Flexible
Phase-Shift,
Multiply/Divide,
and
Delay
Capabilities
Wide Input Frequency Range (1.5 MHz to 350 MHz)
SRAMs and FIFOs
Variable-Aspect Ratio 4,608-Bit RAM Blocks (x1, x2, x4,
x9, x18 Organizations Available)
True Dual-Port SRAM (except x18)
24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
Soft ARM7 Core Support in M7 ProASIC3E
Devices
CoreMP7Sd (with debug) and CoreMP7S (without debug)
Table 1
ProASIC3E Product Family
ProASIC3E Devices
A3PE600
A3PE1500
A3PE3000
ARM-Enabled ProASIC3E Devices1
M7A3PE600
M7A3PE1500
M7A3PE3000
System Gates
600 k
1.5 M
3 M
VersaTiles (D-Flip-Flops)
13,824
38,400
75,264
RAM kbits (1,024 bits)
108
270
504
4,608 Bit Blocks
24
60
112
FlashROM Bits
1 k
Secure (AES) ISP
Yes
CCCs with Integrated PLLs2
66
6
VersaNet Globals3
18
I/O Banks
88
8
Maximum User I/Os
270
439
616
Package Pins
PQFP
FBGA
PQ208
FG256, FG484
PQ208
FG484, FG676
PQ208
FG484, FG896
Notes:
1. Refer to the CoreMP7 datasheet for more information.
2. The PQ208 package has six CCCs and two PLLs.
3. Six chip (main) and three quadrant global networks are available.
4. For devices supporting lower densities, refer to the ProASIC3 Flash FPGAs datasheet.
Advanced v0.5
相關(guān)PDF資料
PDF描述
M7A3PE600-FFGG256I FPGA, 600000 GATES, PBGA256
M7A3PE600-FFGG484I FPGA, 600000 GATES, PBGA484
M7A3PE600-FPQ208I FPGA, 600000 GATES, PQFP208
M7A3PE600-FPQG208I FPGA, 600000 GATES, PQFP208
M7R-R63FAJFREQ CRYSTAL OSCILLATOR, CLOCK, 80.001 MHz - 125 MHz, CMOS/TTL OUTPUT
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