參數(shù)資料
型號： M7A3PE600-FFG256I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA256
封裝： 1 MM PITCH, FBGA-256
文件頁數(shù)： 128/168頁
文件大小： 1335K
代理商： M7A3PE600-FFG256I
ProASIC3E Flash Family FPGAs
2- 50
Advanced v0.5
User I/O Naming Convention
Due to the comprehensive and flexible nature of ProASIC3E device user I/Os, a naming scheme is used to show the
details of the I/O (Figure 2-36). The name identifies to which I/O bank it belongs, as well as the pairing and pin polarity
for differential I/Os.
I/O Nomenclature = Gmn/IOuxwByVz
Gmn is only used for I/Os that also have CCC access—i.e., global pins.
G
= Global
m
= Global pin location associated with each CCC on the device: A (northwest corner), B (northeast corner), C (east
middle), D (southeast corner), E (southwest corner), and F (west middle)
n
= Global input MUX and pin number of the associated Global location m, either A0, A1,A2, B0, B1, B2, C0, C1, or
C2. Figure 2-14 on page 2-16 shows the three input pins per each clock source MUX at the CCC location m.
u
= I/O pair number in the bank, starting at 00 from the northwest I/O bank and proceeds in a clockwise direction.
x
= P (Positive) or N (Negative) for differential pairs, or R (Regular—single-ended) for the I/Os that support single-
ended and voltage-referenced I/O standards only.
w
= D (Differential Pair) or P (Pair) or S (Single-Ended). D (Differential Pair) if both members of the pair are bonded
out to adjacent pins or are separated only by one GND or NC pin; P (Pair) if both members of the pair are
bonded out but do not meet the adjacency requirement; or S (Single-Ended) if the I/O pair is not bonded out.
For Differential (D) pairs, adjacency for ball grid packages means only vertical or horizontal. Diagonal
adjacency does not meet the requirements for a true differential pair.
B
= Bank
y
= Bank number [0..7]. The bank number starts at 0 from northwest I/O bank and proceeds in a clockwise direction.
V
= VREF
z
= VREF minibank number [0...4]. A given voltage-referenced signal spans 16 pins (typically) in an I/O bank. Voltage
banks may have multiple VREF minibanks.
Figure 2-36 User I/O Naming Conventions of ProASIC3E Devices
A3PE600
CCC/PLL
“F”
CCC/PLL
“C”
CCC/PLL
“D”
CCC/PLL
“B”
CCC/PLL
“A”
CCC/PLL
“E”
Bank 0
Bank 1
Bank 5
Bank 4
JT
A
G
Ba
n
k
3
Ba
n
k
2
JTAG
Ba
n
k
6
Ba
n
k
7
A3PE600
CCC/PLL
“F”
CCC/PLL
“C”
CCC/PLL
“D”
CCC/PLL
“B”
CCC/PLL
“A”
CCC/PLL
“E”
Bank 0
Bank 1
Bank 5
Bank 4
JT
A
G
Ba
n
k
3
Ba
n
k
2
JTAG
Ba
n
k
6
Ba
n
k
7
A3PE600
A3PE1500
A3PE3000
CCC/PLL
'A'
Bank 0
Bank 1
Bank 5
Bank 4
JT
A
G
Ba
n
k
3
Ba
n
k
2
JTAG
Ba
n
k
6
Ba
n
k
7
CCC/PLL
'F'
CCC/PLL
'E'
CCC/PLL
'D'
CCC/PLL
'C'
CCC/PLL
'B'
GNDQ
VMV7
VMV6
GNDQ
VMV
0
G
NDQ
GN
D
GN
D
G
NDQ
VMV
1
VM
V4
TM
S
TD
I
TC
K
GN
D
Q
GN
D
GN
D
GN
D
Q
VM
V5
V
CC
V
CC
V
COMPLF
V
CCPLF
V
COMPLE
V
CCPLE
V
COMPLA
V
CCPLA
GND
V
CCIB7
V
CCIB6
GND
V
CC
V
CC
V
CCI
B0
V
CC
V
CCI
B1
V
CC
V
CCI
B4
V
CCI
B5
V
CC
GNDQ
VMV2
GND
TRST
TDO
VMV3
GNDQ
V
COMPLB
V
COMPLC
V
CCPLB
V
CCPLC
V
JTAG
V
CC
V
CC
V
COMPLD
V
PUMP
V
CCPLD
V
CCIB2
GND
V
CC
V
CCIB3
相關(guān)PDF資料
PDF描述
M7A3PE600-FFG484I FPGA, 600000 GATES, PBGA484
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