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參數(shù)資料
| 型號(hào)： | M66291GP |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 75/126頁 |
| 文件大?。?/td> | 810K |
| 代理商： | M66291GP |
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MITSUBISHI <DIGITAL ASSP>
M66291GP
2. Registers
USB -48
Ver.1.0 Apr.9 2001
(2) IVAL (IN Buffer Set/OUT Buffer Status) Bit (b13)
This bit indicates valid value when the E0req bit of this register is set to “0”.
lWhen set to control write transfer (ISEL bit = “0”)
When this bit is set to “1”, the buffer is at CPU side and can be read.
This bit is set to “1” at completion of receiving data.
The conditions of receive completion depend on the CTRW bit.
When this bit is set to “1”, the EPB_RDY bit is set to “1” (buffer ready interrupt occurs).
This bit is cleared to “0” due to one of the reasons as follows:
Reads out all the data received in the CPU side buffer.
Writes “1” to the BCLR bit.
Note:
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
lWhen set to control read transfer (ISEL bit = “1”)
When this bit is set to “0”, the buffer is at CPU side and can be written.
This bit is cleared to “0” due to one of the reasons as follows:
Transmits completely SIE side buffer.
Writes “1” to the BCLR bit.
The transmit completion is changed by the CTRR bit.
When this bit is set to “0” if the EPB_EMPE bit is set to “1”, the EPB_EMP_OVR bit is set to “1”
(buffer empty/size over error interrupt occurs).
This bit is set to “1” due to one of the reasons as follows:
Completely writes the transmit data to CPU side buffer.
Writes “1” to this bit.
When “1” is written to this bit, the write is forcibly completed. When some written data
exists in the buffer, that data is transmitted as the short packet. Here, if the buffer is
empty or cleared, the zero-length packet is transmitted. The buffer can be cleared using the
BCLR bit. Further, the zero-length packet can be transmitted by writing “1” simultaneously
to this bit and to the BCLR bit. In this case the buffer is cleared by setting “1” to BCLR bit,
and this bit is cleared to “0” after the zero-length packet is transmitted.
The write completion also is changed by the CTRR bit.
Note:
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
(3) BCLR (Buffer Clear) Bit (b12)
This bit clears the data written to the CPU side buffer.
lWhen set to control write transfer (ISEL bit = “0”)
When the IVAL bit is set to “1”, the following operations are executed by writing “1” to this bit:
Clears CPU side buffer.
Clears the IVAL bit of this register.
Clears the ODLN bits of this register.
lWhen set to control read transfer (ISEL bit = “1”)
When the IVAL bit is set to “0”, the following operations are executed by writing “1” to this bit:
Clears CPU side buffer.
Further, the zero-length packet can be transmitted by writing “1” simultaneously to this bit and to
the IVAL bit. For details, refer to “IVAL bit”.
When the IVAL bit is set to “1”, the following operations are executed by writing “1” to this bit:
Clears SIE side buffer (Unlike the other endpoints, the SIE side buffer can also be cleared
by this bit).
Clears the IVAL bit of this register.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
| M66291HP#200D | 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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