參數(shù)資料
型號: M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: LQFP-48
文件頁數(shù): 70/126頁
文件大小: 810K
代理商: M66291GP
MITSUBISHI <DIGITAL ASSP>
M66291GP
2. Registers
USB -44
Ver.1.0 Apr.9 2001
2.23 EP0_FIFO Select Register
s
EP0_FIFO Select Register (EP0_FIFO_SELECT)
<Address : H’30>
b15
14
13
12
11
10
9876543
21
b0
RCNT
Octl
BSWP
ISEL
0
-
--
-
--
-
--
-
--
-
--
-
--
<H/W reset : H'0000>
<S/W reset : ->
<USB bus reset : ->
b
Bit name
Function
R
W
15
RCNT
Read Count Mode
0:
The ODLN bits are cleared by reading all receive data
1:
The ODLN bits are counted down by reading receive data
14~11
Reserved. Set it to “0”.
00
10
Octl
Register 8-Bit Mode
0 :
EP0_FIFO Data Register is 16-bit mode
1 :
EP0_FIFO Data Register is 8-bit mode
9~8
Reserved. Set it to “0”.
00
7BSWP
Byte Swap Mode
0 :
Byte is treated as little ENDIAN
1 :
Byte is treated as big ENDIAN
6~1
Reserved. Set it to “0”.
00
0ISEL
Buffer Select
0 :
Control write transfer
1 :
Control read transfer
(1) RCNT (Read Count Mode) Bit (b15)
This bit sets the countdown methods of the ODLN bits at the time of reading the EP0_FIFO Data Register.
When this bit is set to “0”, the ODLN bit value does not change in spite of reading the data from the
EP0_FIFO Data Register, and is cleared to H’0 when all data is read out.
When this bit is set to “1”, the ODLN bit values are counted down every time the data is read from the
EP0_FIFO Data Register. Here, the down-count value differs as shown below depending on whether the
EP0_FIFO Data Register is set to 8-bit mode or 16-bit mode:
8-bit mode
: Down-count per “-1”
16-bit mode
: Down-count per “-2”
Note
: Use the *HWR/*BYTE pin or the Octl bit of this register for setting the 8-bit/16-bit mode.
(2) Octl (Register 8-Bit Mode) Bit (b10)
This bit sets the access mode of the EP0_FIFO Data Register.
When this bit is set to “0”, the EP0_FIFO Data Register is set to 16-bit mode, and all bits of the EP0_FIFO
Data Register are valid.
When this bit is set to “1”, the EP0_FIFO Data Register is set to 8-bit mode, and the upper-order 8 bits of the
EP0_FIFO Data Register (b15 to b8) are invalid.
Set this bit before receiving the data.
When set to control write transfer (ISEL bit = “0”), change this bit before receiving the data. When set to
control read transfer (ISEL bit = “1”), if the E0req bit indicates “1”, do not change this bit.
This bit becomes invalid (fixed to 8-bit mode) when the mode is set to 8-bit by *HWR/*BYTE pin.
In such case, this bit is read “0”.
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