參數(shù)資料
型號(hào): M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: LQFP-48
文件頁數(shù): 55/126頁
文件大?。?/td> 810K
代理商: M66291GP
MITSUBISHI <DIGITAL ASSP>
M66291GP
2. Registers
USB -30
Ver.1.0 Apr.9 2001
Powered
state
(DVSQ bits ="000")
SET_ADDRESS excecution
(W hen SADR bit="1", DVST bit is set to "1")
USB bus reset detection
(W hen URST bit="1", DVST bit is set to "1")
Resume (RESM bit is set to "1")
Default
state
(DVSQ bits="001")
Configured
state
(DVSQ bits="011")
Suspended
state
(DVSQ bits="100")
Address
state
(DVSQ bits="010")
Suspended
state
(DVSQ bits="111")
Suspended
state
(DVSQ bits="101")
Suspended
state
(DVSQ bits="110")
Suspend detection
(W hen SUSP bit="1", DVST bit is set to "1")
Resume (RESM bit is set to "1")
SET_CO NFIGURAT IO N excecution[ConfigurationValue=0]
(
W hen SCFG bit="1", DVST bit is set to "1")
Suspend detection
(W hen SUSP bit="1", DVST bit is set to "1")
Resume (RESM bit is set to "1")
Suspend detection
(W hen SUSP bit="1", DVST bit is set to "1")
Suspend detection
(W hen SUSP bit="1", DVST bit is set to "1")
Resume (RESM bit is set to "1")
USB bus reset detection
(W hen URST bit="1", DVST bit is set to "1")
Note : The URST, SADR, SCFG and SUSP bits (Interrupt Enable Register 0) in the parenthesis set enable/disable to set the DVST bit to "1" for the
corresponding stage transition. There is no bit to set enable/disable to set the RESM bit to "1".
The stage transition takes place even if these bits are inhibited to set to "1".
SET_CONFIGURATION excecution[ConfigurationValue= 0]
(W hen SCFG bit="1", DVST bit is set to "1")
/
Figure 2.6 Device State Transition
(11) VALID (Setup Packet Detect) Bit (b3)
This bit indicates that the setup token has been received.
When the setup token is completely received, this bit is set to “1”.
When this bit is set to “1”, the writing to EP0_PID/CCPL bits of EP0_FIFO Control Register is ignored.
At the time of receiving the setup token, the interrupt has not occurred (the interrupt occurs only after the
termination of setup stage).
This bit is cleared to “0” by writing “0”.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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