參數(shù)資料
型號: M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: LQFP-48
文件頁數(shù): 41/126頁
文件大小: 810K
代理商: M66291GP
MITSUBISHI <DIGITAL ASSP>
M66291GP
2. Registers
USB -17
Ver.1.0 Apr.9 2001
2.7 Polarity Set Register
s
Polarity Set Register (POLARITY_CNT)
<Address : H’0E>
b15
14
13
12
11
10
9876543
21
b0
VB01
RM01
SF01
DS01
CT01
BE01
NR01
RD01
RDYM
INTL
INTA
0
000000
0
000
0
000000
0
000
-
-------
-
---
<H/W reset : H'0000>
<S/W reset : H’0000>
<USB bus reset : ->
b
Bit name
Function
R
W
15
VB01
Vbus Interrupt Assign
0 :
Assigns to INT0 pin
1 :
Assigns to INT1 pin (Note)
14
RM01
Resume Interrupt Assign
0 :
Assigns to INT0 pin
1 :
Assigns to INT1 pin (Note)
13
SF01
SOF Detect Interrupt Assign
0 :
Assigns to INT0 pin
1 :
Assigns to INT1 pin (Note)
12
DS01
Device State Transition Interrupt Assign
0 :
Assigns to INT0 pin
1 :
Assigns to INT1 pin (Note)
11
CT01
Control Transfer Transition Interrupt Assign
0 :
Assigns to INT0 pin
1 :
Assigns to INT1 pin (Note)
10
BE01
Buffer Empty/Size Over Error Interrupt Assign
0 :
Assigns to INT0 pin
1 :
Assigns to INT1 pin (Note)
9NR01
Buffer Not Ready Interrupt Assign
0 :
Assigns to INT0 pin
1 :
Assigns to INT1 pin (Note)
8RD01
Buffer Ready Interrupt Assign
0 :
Assigns to INT0 pin
1 :
Assigns to INT1 pin (Note)
7~3
Reserved. Set it to “0”.
00
2RDYM
Buffer Ready Mode
0 :
Clears the EPB_RDY bits by reading/writing all data of
buffer
1 :
Clears the EPB_RDY bits by writing "0" to EPB_RDY bit
1INTL
Interrupt Output Sense
0 :
Edge sensitive output
1 :
Level sensitive output
0INTA
Interrupt Polarity
0 :
"L" active or change from “H” to “L”
1 :
"H" active or change from "L" to "H"
Note : In order to allocate the interrupt output signal to the INT1/SOF pin, set the SOF signal output to “disable” (SOFOE bit =
“0”).
(1) VB01 (Vbus Interrupt Assign) Bit (b15)
This bit selects the pin to output the Vbus interrupt signal.
(2) RM01 (Resume Interrupt Assign) Bit (b14)
This bit selects the pin to output the resume interrupt signal.
(3) SF01 (SOF Detect Interrupt Assign) Bit (b13)
This bit selects the pin to output the SOF detect interrupt signal.
(4) DS01 (Device State Transition Interrupt Assign) Bit (b12)
This bit selects the pin to output device state transition interrupt signal.
(5) CT01 (Control Transfer Transition Interrupt Assign) Bit (b11)
This bit selects the pin to output the control transfer transition interrupt signal.
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