參數(shù)資料
型號: M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 77/126頁
文件大?。?/td> 893K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 54 of 122
2.27 CPU_FIFO Select Register
CPU_FIFO Select Register (CPU_FIFO_SELECT)
<Address : H’40>
b15
14
13
12
11
10
9876
54321
b0
RCNT
RWND
BSWP
Octl
CPU_EP
0
00
0
00
0
-
--
-
--
-
<H/W reset : H'0000>
<S/W reset : ->
<USB bus reset : ->
b
Bit name
Function
R
W
15
RCNT
Read Count Mode
0:
The CPU_DTLN bits are cleared by reading all receive
data
1:
The CPU_DTLN bits are counted down by reading receive
data
14~13
Reserved. Set it to “0”.
00
12
RWND
Buffer Rewind
<When set to OUT buffer>
Write
0 :
Invalid (Ignored when written)
1 :
Clears the buffer reading pointer
<When set to IN buffer>
Write
0 :
Invalid (Ignored when written)
1 :
Clears the buffer writing pointer
0
11~8
Reserved. Set it to “0”.
00
7
BSWP
Byte Swap Mode
0 :
Byte is treated as little ENDIAN
1 :
Byte is treated as big ENDIAN
6Octl
Register 8-Bit Mode
0 :
CPU_FIFO Data Register is 16-bit mode
1 :
CPU_FIFO Data Register is 8-bit mode
5~4
Reserved. Set it to “0”.
00
3~0
CPU_EP
CPU Access Endpoint Designate
0001 :EP1 (Endpoint 1)
0010 :EP2 (Endpoint 2)
0011 :EP3 (Endpoint 3)
0100 :EP4 (Endpoint 4)
0101 :EP5 (Endpoint 5)
0110 :EP6 (Endpoint 6)
Other than those above : Invalid
(1) RCNT (Read Count Mode) Bit (b15)
This bit sets the countdown methods of the CPU_DTLN bits at the time of reading the CPU_FIFO Data
Register.
When this bit is set to “0”, the CPU_DTLN bit value does not change in spite of reading the data from the
CPU_FIFO Data Register, and is cleared to H’0 when all data is read out.
When this bit is set to “1”, the CPU_DTLN bit values are counted down every time the data is read from the
CPU_FIFO Data Register. Here, the down-count value differs as shown below depending on whether the
CPU_FIFO Data Register is set to 8-bit mode or 16-bit mode:
8-bit mode
: Down-count per “-1”
16-bit mode
: Down-count per “-2”
Note
: Use the *HWR/*BYTE pin or the Octl bit of this register for setting the 8-bit/16-bit mode.
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