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| 型號(hào)： | M66291GP |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP48 |
| 封裝： | 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁(yè)數(shù)： | 106/126頁(yè) |
| 文件大小： | 893K |
| 代理商： | M66291GP |
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M66291GP/HP
Rev 1.01 2004.11.01 page 80 of 122
This bit is valid at continuous transmit/receive mode (EPi_RWMD bit = “1”) when set to IN buffer (EPi_DIR
bit = “1”). Set to “0” for the other modes.
In case of the completion of SIE side buffer transmit, if the IVAL bit is set to “0”, the zero-length packet
automatically transmitted in the last under the condition as follows:
When the buffer size set by the EPi_Buf_siz bit is the integral multiple of the size set by the
EPi_MXPS bits.
In case of the continuous transmit/receive mode, the data equivalent to the size set by the EPi_MXPS bits is
automatically transmitted several times before transmitting the data equivalent to the size set by the
EPi_Buf_siz bit.
(3) EPi_ACLR (OUT Buffer Auto-Clear Mode) Bit (b11)
When set to OUT buffer (EPi_DIR bit = “0”), all buffers both of CPU and SIE sides are cleared by setting “1” to
this bit.
This bit does not get automatically cleared to “0” even after the buffers are cleared.
When this bit is set to “1”, if BUF is set to the EPi_PID bits, the NAK response is not executed against the
received OUT token. Instead, the ACK response is sent to the host after receiving the data. The received data
is not written to the buffer. Further, with the EPi_PID bits set to NAK/STALL, the NAK/STALL response is
executed.
When set to IN buffer (EPi_DIR bit = “1”), only the SIE side buffer and the buffer with the writing completed
(the buffer when IVAL bit = “1”) are cleared by setting “1” to this bit.
When this bit is set to “1”, if BUF is set to the EPi_PID bits, the NAK response is given against the received IN
token. Further, with the EPi_PID bits set to NAK/STALL, the NAK/STALL response is executed.
Note:
When set to IN buffer, make sure to set the response PID to NAK (EPi_PID bits = “00”) before setting this bit to
“1”.
(5) EPi_Octl (Register 8-Bit Mode) Bit (b10)
This bit has the same function as the Octl bit of the CPU_FIFO Select Register or the Octl bit of the Dn_FIFO
Select Register. Please refer to the items of these registers.
(6) EPi_MXPS (Maximum Packet Size) Bits (b9~b0)
These bits set the upper limit (byte count) of the data transmitted and received in one packet transfer.
Set the wMaxPacketSize value transmitted to the host.
In case of transmitting, the data equivalent to the size set by these bits is read out from the buffer for transmit.
If the buffer does not have the data equivalent to the set by these bits, the data is transmitted as the short
packet.
In case of receiving, the received data equivalent to the size set by these bits is written to the buffer. In case
the received data exceeds the size set by these bits, the following bit is set to "1":
The EPB_EMP_OVR bit
(buffer empty/size-over error interrupt occurs when the EPB_EMPE bit is set to “1”).
Note:
Set this bit after setting the response PID to NAK (EPi_PID bits = “00”).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M66291GP#201 | 制造商:Renesas Electronics Corporation 功能描述:IC ASSP USB2.0 DEVICE CONTROLLER 48LQFP |
| M66291GP#RB0S | 功能描述:IC USB CONTROLLER GEN-PUR 48LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
| M66291GPRB0S | 制造商:Renesas Electronics Corporation 功能描述:USB2.0 Device Controller,LQFP48 |
| M66291HP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:ASSP (USB2.0 Device Controller) |
| M66291HP#200D | 功能描述:IC USB CONTROLLER GEN-PUR 52VQFN RoHS:否 類別:集成電路 (IC) >> 接口 - 控制器 系列:- 標(biāo)準(zhǔn)包裝:4,900 系列:- 控制器類型:USB 2.0 控制器 接口:串行 電源電壓:3 V ~ 3.6 V 電流 - 電源:135mA 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:36-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:36-QFN（6x6） 包裝:* 其它名稱:Q6396337A |
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