參數(shù)資料
型號(hào): M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁(yè)數(shù): 71/126頁(yè)
文件大?。?/td> 893K
代理商: M66291GP
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M66291GP/HP
Rev 1.01 2004.11.01 page 49 of 122
(1) EP0_PID (Response PID) Bits (b15~b14)
These bits set the PID for response to the host at data/status stage of the control transfer.
At setup stage, the ACK response is executed irrespective of these bits.
Writing these bits are ignored when the VALID bit is equal to“1”.
When these bits are set to “00”
Data stage
: NAK response
Status stage
: NAK response
When these bits are set to “01”
<When set to control write transfer (ISEL bit = “0”)>
Data stage
: ACK response after receiving the data if the SIE side buffer can be ready to
receive
: NAK response if the SIE side buffer is not ready to receive
In case the SIE side buffer is not ready to receive, the EPB_NRD bit is
set to “1” when OUT token is received.
Status stage
: Depends on CCPL bit
<When set to control read transfer (ISEL bit = “1”)>
Data stage
: Transmits the data if the SIE side buffer is not ready to transmit
: NAK response if the SIE side buffer is not ready to transmit
In case the SIE side buffer is not ready to transmit, the EPB_NRD bit is
set to “1” when IN token is received.
Status stage
: Depends on CCPL bit
When these bits are set to “1x”
Data stage
: STALL response
In case the SIE side buffer is not ready to receive/transmit, the
EPB_NRD bit is set to “1” when OUT token is received.
Status stage
: STALL response
The NAK response is not executed even if these bits are set to “00” when the data is being received at data
stage. The settings of these bits are reflected from the next transaction.
Similarly, the transmission is not interrupted even if these bits are set to “00” when the data is being
transmitted at data stage.
Further, these bits are automatically set to the values below when the following states occur:
When setup token is received
"00" (NAK)
When the request set to automatic response (SET_ADDRESS or SET_CONFIGURATION) is received
"01" (BUF)
The CCPL bit also is automatically set to “1” and transmits the zero-length packet at the succeeding
status stage (IN transaction).
When sequence error occurs (CTSQ bits are set to “110”)
"1x" (STALL)
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