參數(shù)資料
型號: M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 55/126頁
文件大?。?/td> 893K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 34 of 122
2.13 Interrupt Status Register 1
Interrupt Status Register 1 (INT_STATUS1)
<Address : H’1A>
b15
14
13
12
11
10
9876
54321
b0
EPB_RDY
0
00
-
<H/W reset :H'0000>
<S/W reset : H'0000>
<USB bus reset : ->
b
Bit name
Function
R
W
15~7
Reserved. Set it to “0”.
00
6~0
EPB_RDY
Buffer Ready Interrupt
Read
0 :
No occurrence of interrupt
1 :
Occurrence of interrupt
Write
<When RDYM bit is set to "0">
Invalid (Ignored when written)
<When RDYM bit is set to "1">
0 :
Clear interrupt clear
1 :
Invalid (Ignored when written)
b6 corresponds to EP6, ---b1 corresponds to EP1 and b0
corresponds to EP0.
(1) EPB_RDY (Buffer Ready Interrupt) Bits (b6~b0)
The bit corresponding to each endpoint is set to “1” with the buffer at “ready” state.
The ready state refers to the state when CPU or DMAC can read or write the CPU side buffer. When the EPB_RE
bit is set to “1”, if this bit is set to “1”, the INTR bit is set to “1”, causing the buffer ready interrupt to occur.
Setting “1”/clearing to ”0” to this bit differs according to the endpoint and transfer direction as shown below:
Note :
Refer to “3.2 FIFO Buffer” for CPU/SIE side.
Endpoint 0
When set to control write transfer (ISEL bit = “0”)
The condition for this bit to be set to “1” is as follows:
When the IVAL bit of the EP0_FIFO Control Register changes from “0” to “1”
The condition for this bit to be cleared to “0” differs according to the RDYM bit:
RDYM bit = “0” : When the IVAL bit of the EP0_FIFO Control Register changes from
“1” to“0”
RDYM bit = “1” : Writes “0” to this bit
When set to control read transfer (ISEL bit = “1”)
This bit is not set to “1” (Refer to “EPB_EMP_OVR bit”).
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