參數(shù)資料
型號(hào): M66291GP
元件分類: 總線控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP48
封裝: 7 X 7 MM, 0.50 MM PITCH, PLASTIC, LQFP-48
文件頁數(shù): 110/126頁
文件大小: 893K
代理商: M66291GP
M66291GP/HP
Rev 1.01 2004.11.01 page 84 of 122
3.2.3
Buffer State and IVAL Bit
(1) Buffer state and IVAL bit of the OUT buffer
The relation between buffer state and IVAL bit is shown in Figure 3.2 when the buffer is set to OUT (set by
the EPi_DIR bit/ISEL bit).
The single/double buffer mode is set by the EPi_DBLB bit. The double buffer mode cannot be set at endpoint 0.
<W hen set to single buffer mode>
CPU bus
Empty
W hen set to O UT buffer
SIE bus
IVAL bit ="0"
Receive
data
Receive data
IVAL bit ="1"
Receive
data
IVAL bit ="0"
Empty
<W hen set to double buffer mode>
Empty
SIE bus
IVAL bit ="0"
Receive
data
Receive data
IVAL bit ="1"
Empty
IVAL bit ="0"
Receive data
Empty
Receive
data
R eceiv e com pletion (Note 2)
Receive
data
Receive data
Empty
Receive data
Empty
IVAL bit ="1"
(EPB_RDY bit is set to "1")
IVAL bit ="0"
IVAL bit ="1"
(EPB_RDY bit is set to "1")
Receive
data
Empty
IVAL bit ="1"
IVAL bit ="0"
IVAL bit ="1"
(EPB_RDYbit is set to"1")
Note 1. R esponse to the host when EP0_PID /EPn_PID bits are set to "01(BUF)".
Note 2. About the receives completion, refer to the follows:
Endpoint 0
CT R W bit of C ontrol T ransfer Control Register
O thers endpoint 0
EPnRW MD bit of EPn C onfiguration R egister
CPU bus
Accessable
Not accessable
Read com pletion
Receiv e com pletion (Note 2)
Read com pletion
SIE side buffer
C PU side buffer
SIE side buffer CPU side buffer
Receive data
IVAL bit ="0"
Empty
IVAL bit ="0"
R esponse (Note 1)
AC K
NAK
AC K
NAK
Response (Note 1)
AC K
NAK
AC K
NAK
AC K
R eceive com pletion (N ote 2)
Figure 3.2 Relation between Buffer State and IVAL Bit (when set to OUT buffer)
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