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參數(shù)資料
| 型號： | M5XXLFXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 500 SERIES, PLL BASED CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 |
| 封裝： | 3 X 3 MM, 0.60 MM HEIGHT, LEAD FREE, MO-220, QFN-16 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 312K |
| 代理商： | M5XXLFXI |
MoBL Clock
M200/M500
Document #: 001-29139 Rev. *A
Page 4 of 14
General Description
2 Configurable PLLs
The MoBL Clock M200/M500 Family of products are two-PLL
Clock Generator ICs designed for cell phone, portable, or
consumer electronics applications. It can be used to generate
two independent output frequencies ranging from 3 to 50MHz
from a single input reference clock.
I2C Programming
The MoBL Clock M200 and M500 have a serial I2C interface
that programs the configuration memory array to synthesize
output frequencies by programmable output divider, spread
characteristics, and drive strength. I2C can also be used for
in-system control of these programmable features.
Input Reference Clocks
The input to the M200 and M500 are designed to use an external
reference clock with a frequency range of 1 MHz to 48 MHz at
the EXCLKIN pin. The voltage level for the input reference clock
used must follow VDD voltage used for the device as shown in
the DC and AC specifications.
Output Power Supply Options
There are three clock outputs CLK1, CLK2, and CLK3 driven by
three separate output power supplies: VDD_CLK1, VDD_CLK2,
and VDD_CLK3 respectively. Different voltage level for each of
these power supplies can be used and they can be any of 1.5V,
1.8V, 2.5V, 3.0V, or 3.3V giving user multiple choice of output
clock voltage levels.
Output Source Selection
These devices have three clock outputs, CLK1, CLK2 and CLK3.
There are three available clock sources for these outputs. These
clock sources are: PLL1, PLL2, or EXCLKIN. Output clock
source selection is done using three out of three crossbar switch.
Thus, any one of these three available clock sources can be
arbitrarily selected for the clock outputs. This gives user a flexi-
bility to have up to two independent clocks and a Reference clock
output.
Spread Spectrum Control
The PLL2 has spread spectrum capability for EMI reduction in
the system. The device uses a Cypress proprietary PLL and
Spread Spectrum Clock (SSC) technology to synthesize and
modulate the frequency of the PLL. The spread spectrum feature
can be turned on or off by I2C device programming. It can be
factory programmed to either center spread range from ±0.125%
to ±2.50%, or down spread range from –0.25% to –5.0%, with
Lexmark or Linear modulation profile.
PD#/OE Mode
PD#/OE input (Pin 4) can be programmed to operate as either
power down (PD#) or output enable (OE) mode. Note that power
down shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings. The
PD# turn-on time is limited by the turn-on time of the PLLs.
Disabled outputs are first driven to a low state before turning off.
When off, they are held low by internal weak resistors (~160k
ohms)
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 4). Individual
clock outputs can be programmed to be sensitive to this OE pin.
Keep Alive Mode
By activating the device in the Keep Alive Mode, power down
mode is changed to power saving mode, which disables all PLLs
and outputs, but preserves the contents of the volatile registers.
Thus, any configuration changes made via the I2C interface are
preserved. By deactivating the Keep Alive Mode, I2C memory is
not preserved during power down, but power consumption is
reduced relative to the Keep Alive Mode.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 3 shows the typical rise
and fall times for different drive strength settings.
Generic Configuration and Custom Frequency
The device is available with Factory Specific programmed
frequencies as shown in the Ordering Information page. This
factory specific programmed part can be used for the device
evaluation purposes. The MoBL Clock can be custom
programmed to any desired frequencies and listed features. For
customer specific programming and I2C programmable memory
bitmap definitions, please contact local Cypress Field Appli-
cation Engineer (FAE) or sales representative.
Table 3. Output Drive Strength
Output Drive Strength
Rise/Fall Time (ns)
(Typical Value)
Low
6.8
Mid Low
3.4
Mid High
2.0
High
1.0
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