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參數(shù)資料
| 型號(hào)： | M5XXLFXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 500 SERIES, PLL BASED CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 |
| 封裝： | 3 X 3 MM, 0.60 MM HEIGHT, LEAD FREE, MO-220, QFN-16 |
| 文件頁(yè)數(shù)： | 8/14頁(yè) |
| 文件大?。?/td> | 312K |
| 代理商： | M5XXLFXI |
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MoBL Clock
M200/M500
Document #: 001-29139 Rev. *A
Page 3 of 14
MoBL Clock M500
Figure 2. Pin Diagram - 16 LD QFN
VDD_CLK2
8
MoBL Clock M500
16 LD QFN
16
15
14
13
1
2
3
4
6
7
9
10
11
12
VSS
CLK2
DNU
V
S
C
L
K
3
VD
D
CLK1
PD#/OE
5
VSS
SD
A
SC
L
VDD_CLK3
VDD_CLK1
EX
C
L
KI
N
Table 2. Pin Definitions - MoBL Clock M500 Family (VDD = 2.5V, 3.0V or 3.3V Supply)
Pin Number
Name
IO
Description
1
VSS
Power
GND
2
CLK1
Output
Programmable Clock Output. Output voltage depends on
VDD_CLK1 voltage
3
VDD_CLK1
Power
Power Supply for CLK1: 1.5V/1.8V/2.5V/3.0V/3.3V
4
PD#/OE
Input
Multifunction Programmable pin: Output Enable or Power Down
Modes
5
VSS
Power
GND
6SCL
Input
I2C-Bus Clock Line
7
SDA
Input/Output
I2C-Bus Data Line
8
VSS
Power
GND
9
CLK2
Output
Programmable Clock Output. Output voltage depends on
VDD_CLK2 voltage
10
VDD_CLK2
Power
Power Supply for CLK2: 1.5V/1.8V/2.5V/3.0V/3.3V
11
VDD_CLK3
Power
Power Supply for output CLK3: 1.5V/1.8V/2.5V/3.0V/3.3V
12
DNU
Do Not Use this pin
13
VSS
Power
GND
14
CLK3
Output
Programmable Clock Output. Output voltage depends on
VDD_CLK3 voltage
15
VDD
Power
Power Supply: 2.5V/3.0V/3.3V
16
EXCLKIN
Input
2.5V/3.0V/3.3V external Reference Clock
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