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參數(shù)資料
| 型號： | M5XXLFXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 500 SERIES, PLL BASED CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 |
| 封裝： | 3 X 3 MM, 0.60 MM HEIGHT, LEAD FREE, MO-220, QFN-16 |
| 文件頁數(shù)： | 11/14頁 |
| 文件大?。?/td> | 312K |
| 代理商： | M5XXLFXI |
MoBL Clock
M200/M500
Document #: 001-29139 Rev. *A
Page 6 of 14
Figure 3. Data Transfer Sequence on the Serial Bus
Figure 4. Data Frame Architecture
Figure 5. Data Valid and Data Transition Periods
SCL
START
Condition
SDA
STOP
Data may
Address or
Acknowledge
Valid
be changed
Condition
SDA
Write
Start Signal
Device
Address
7-bit
R/W = 0
1 Bit
8-bit
Register
Address
Slave
1 Bit
ACK
Slave
1 Bit
ACK
8-bit
Register
Data
Stop Signal
Multiple
Contiguous
Registers
Slave
1 Bit
ACK
8-bit
Register
Data
(XXH)
(XXH+1)
Slave
1 Bit
ACK
8-bit
Register
Data
(XXH+2)
Slave
1 Bit
ACK
8-bit
Register
Data
(FFH)
Slave
1 Bit
ACK
8-bit
Register
Data
(00H)
Slave
1 Bit
ACK
Slave
1 Bit
ACK
SDA
Read
Start Signal
Device
Address
7-bit
R/W = 1
1 Bit
8-bit
Register
Data
Slave
1 Bit
ACK
Slave
1 Bit
ACK
Stop Signal
SDA
Read
Start Signal
Device
Address
7-bit
R/W = 0
1 Bit
8-bit
Register
Address
Slave
1 Bit
ACK
Slave
1 Bit
ACK
7-bit
Device
Stop Signal
Multiple
Contiguous
Registers
Master
1 Bit
ACK
8-bit
Register
Data
Master
1 Bit
ACK
(XXH)
Master
1 Bit
ACK
8-bit
Register
Data
(XXH+1)
Master
1 Bit
ACK
8-bit
Register
Data
(FFH)
Master
1 Bit
ACK
8-bit
Register
Data
(00H)
Master
1 Bit
ACK
Master
1 Bit
ACK
Current
Address
Read
Address
+R/W=1
Repeated
Start bit
SDA
SCL
Data Valid
Transition
to next Bit
CLKLOW
CLKHIGH
VIH
VIL
tSU
tDH
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