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參數(shù)資料
| 型號： | M5XXLFXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 500 SERIES, PLL BASED CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 |
| 封裝： | 3 X 3 MM, 0.60 MM HEIGHT, LEAD FREE, MO-220, QFN-16 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 312K |
| 代理商： | M5XXLFXI |
MoBL Clock
M200/M500
Document #: 001-29139 Rev. *A
Page 10 of 14
Notes
1. This parameter is configuration dependent. The specified value is for the drive level setting of [1,1].
2. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.
AC Electrical Specifications
The AC Electrical Specifications table for M2xx/M5xx (VDD_CLKX = 1.5V/1.8V/2.5V/3.0/3.3V) family.
Parameter
Description
Conditions
Min
Typ
Max
Unit
FCLK
Clock Output Frequency
All clock outputs
3
–
50
MHz
FREF
Driven Reference Frequency
EXCLKIN Clock
1
–
48
MHz
DC
Output Clock Duty Cycle
Duty Cycle as defined in Figure 9 on
t1/t2, 50% of VDD_CLKX
45
50
55
%
TRF1
Output Clock Rise/Fall Time
Measured from 20% to 80% of
strength [00]
–
6.8
10.0
ns
TRF2
Output Clock Rise/Fall Time
Measured from 20% to 80% of
strength [01]
–3.4
5.0
ns
TRF3
Output Clock Rise/Fall Time
Measured from 20% to 80% of
strength [10]
–2.0
3.0
ns
TRF4
Output Clock Rise/Fall Time
Measured from 20% to 80% of
strength [11]
–1.0
1.5
ns
TCCJ
[1,2]
Cycle-to-cycle Jitter
EXCLKIN = CLKx = 48 MHz, CLOAD
= 15 pF, 2 PLLs and 1 output for each
PLL enabled, drive strength = [11]
–150
–
ps
TLOCK
PLL Lock Time
–
1
3
ms
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