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參數(shù)資料
| 型號(hào)： | M5XXLFXI |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 500 SERIES, PLL BASED CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC16 |
| 封裝： | 3 X 3 MM, 0.60 MM HEIGHT, LEAD FREE, MO-220, QFN-16 |
| 文件頁(yè)數(shù)： | 10/14頁(yè) |
| 文件大小： | 312K |
| 代理商： | M5XXLFXI |
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MoBL Clock
M200/M500
Document #: 001-29139 Rev. *A
Page 5 of 14
I2C Serial Interface
To enhance the flexibility and function of the clock synthesizer, a
two-signal I2C serial interface is provided. This interface is used
to write (and optionally read) control registers that control various
device functions such as enabling individual clock output buffers.
The registers initialize to their default setting upon power up and
therefore, use of this interface is optional. Clock device registers
are normally changed upon system initialization. Any data written
via I2C is volatile and is not retained when the device is powered
down.
The I2C interface uses two signals, SDA and SCL, that operates
up to 400 kbits/s in Read or Write mode. The SDA and SCL
timing and data transfer sequence is shown in Figure 3 on page
6. The basic Write serial format is as follows:
Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock
Acknowledge (ACK); 8-bit Memory Address (MA); ACK; 8-bit
Data; ACK; 8-bit Data in MA+1 if desired; ACK; 8-bit Data in
MA+2; ACK; etc. until STOP Bit. The basic serial format is illus-
trated in Figure 4 on page 6.
Device Address
The device serial interface address is 69H. The device address
is combined with a read/write bit as the LSB and is sent after
each start bit.
Data Valid
Data is valid when the clock is HIGH, and can only be transi-
tioned when the clock is LOW, as illustrated in Figure 5 on page
Data Frame
Every new data frame is indicated by a start and stop sequence,
as illustrated in Figure 6 on page 7.
Start Sequence – SDA going LOW when SCL is HIGH indicates
a Start Frame. Every time a start signal is supplied, the next 8-bit
data must be the device address (seven bits) and a R/W bit,
followed by register address (eight bits) and register data (eight
bits).
Stop Sequence – SDA going HIGH when SCL is HIGH indicates
a Stop Frame. A Stop Frame frees the bus to write to another part
on the same bus or to write to another random register address.
Acknowledge Pulse
During Write Mode, the MoBL Clock M2xx/M5xx responds with
an Acknowledge pulse after every eight bits. This is done by
pulling the SDA line LOW during the N*9th clock cycle, as illus-
trated in Figure 7 on page 7 (N = the number of bytes trans-
mitted). During Read Mode, the master generates the
acknowledge pulse after reading the data packet.
Write Operations
Writing Individual Bytes
A valid write operation must have a full 8-bit register address
after the device address word from the master, which is followed
by an acknowledge bit from the slave (ack = 0/LOW). The next
eight bits must contain the data word intended for storage. After
the receiving the data word, the slave responds with another
acknowledge bit (ack = 0/LOW), and the master must end the
write sequence with a STOP condition.
Writing Multiple Bytes
To write multiple bytes at a time, the master must not end the
write sequence with a STOP condition, but instead sends
multiple contiguous bytes of data to be stored. After each byte,
the slave responds with an acknowledge bit, the same as after
the first byte, and accepts data until the acknowledge bit is
responded to by the STOP condition. When receiving multiple
bytes, the MoBL Clock M2xx/M5xx internally increments the
register address.
Read Operations
Read operations are initiated the same way as Write operations
except that the R/W bit of the slave address is set to ‘1’ (HIGH).
There are three basic read operations: current address read,
random read, and sequential read.
Current Address Read
The MoBL Clock M2xx/M5xx have an onboard address counter
that retains ‘1’ more than the address of the last word accessed.
If the last word written or read was word ‘n’, then a current
address read operation returns the value stored in location ‘n+1’.
When the MoBL Clock M2xx/M5xx receives the slave address
with the R/W bit set to a ‘1’, it issues an acknowledge and
transmits the 8-bit word. The master device does not
acknowledge the transfer, but generates a STOP condition,
which causes the MoBL Clock M2xx/M5xx to stop transmission.
Random Read
Through random read operations, the master may access any
memory location. To perform this type of read operation, first set
the word address. To do this, send the address to the MoBL
Clock M2xx/M5xx as part of a write operation. After the word
address is sent, the master generates a START condition
following the acknowledge. This terminates the write operation
before any data is stored in the address, but not before the
internal address pointer is set. Next, the master reissues the
control byte with the R/W byte set to ‘1’. The MoBL Clock
M2xx/M5xx then issues an acknowledge and transmits the 8-bit
word. The master device does not acknowledge the transfer, but
generates a STOP condition, which causes the MoBL Clock
M200/M500 to stop transmission.
Sequential Read
Sequential read operations follow the same process as random
reads except that the master issues an acknowledge instead of
a STOP condition after transmission of the first 8-bit data word.
This action increments the internal address pointer, and subse-
quently outputs the next 8-bit data word. By continuing to issue
acknowledges instead of STOP conditions, the master serially
reads the entire contents of the slave device memory. When the
internal address pointer points to the FFH register, after the next
increment, the pointer points to the 00H register.
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