參數(shù)資料
型號: M37274MA
廠商: Mitsubishi Electric Corporation
英文描述: Single Chip 8 Bits Microcomputer(8位單片機(jī))
中文描述: 單芯片8位單片機(jī)(8位單片機(jī))
文件頁數(shù): 50/131頁
文件大?。?/td> 2049K
代理商: M37274MA
50
MITSUBISHI MICROCOMPUTERS
M37274MA-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
(10) Address Data Communication
There are two address data communication formats, namely, 7-bit
addressing format and 10-bit addressing format. The respective ad-
dress communication formats is described below.
7-bit addressing format
To meet the 7-bit addressing format, set the 10BIT SAD bit of the
I
2
C control register (address 00F9
16
) to “0.” The first 7-bit address
data transmitted from the master is compared with the high-order
7-bit slave address stored in the I
2
C address register (address
00F7
16
). At the time of this comparison, address comparison of
the RBW bit of the I
2
C address register (address 00F7
16
) is not
made. For the data transmission format when the 7-bit address-
ing format is selected, refer to Figure 52, (1) and (2).
10-bit addressing format
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
I
2
C control register (address 00F9
16
) to “1.” An address compari-
son is made between the first-byte address data transmitted from
the master and the 7-bit slave address stored in the I
2
C address
register (address 00F7
16
). At the time of this comparison, an ad-
dress comparison between the RBW bit of the I
2
C address regis-
ter (address 00F7
16
) and the R/W bit which is the last bit of the
address data transmitted from the master is made. In the 10-bit
addressing mode, the R/W bit which is the last bit of the address
data not only specifies the direction of communication for control
data but also is processed as an address data bit.
When the first-byte address data matches the slave address, the
AAS bit of the I
2
C status register (address 00F8
16
) is set to “1.” After
the second-byte address data is stored into the I
2
C data shift register
(address 00F6
16
), make an address comparison between the sec-
ond-byte data and the slave address by software. When the address
data of the 2nd bytes matches the slave address, set the RBW bit of
the I
2
C address register (address 00F7
16
) to “1” by software. This
processing can match the 7-bit slave address and R/W data, which
are received after a RESTART condition is detected, with the value
of the I
2
C address register (address 00F7
16
). For the data transmis-
sion format when the 10-bit addressing format is selected, refer to
Figure 52, (3) and (4).
(11) Example of Master Transmission
An example of master transmission in the standard clock mode, at
the SCL frequency of 100 kHz and in the ACK return mode is shown
below.
Set a slave address in the high-order 7 bits of the I
2
C address
register (address 00F7
16
) and “0” in the RBW bit.
Set the ACK return mode and SCL = 100 kHz by setting “85
16
” in
the I
2
C clock control register (address 00FA
16
).
Set “10
16
” in the I
2
C status register (address 00F8
16
) and hold
the SCL at the HIGH.
Set a communication enable status by setting “48
16
” in the I
2
C
control register (address 00F9
16
).
Set the address data of the destination of transmission in the high-
order 7 bits of the I
2
C data shift register (address 00F6
16
) and set
“0” in the least significant bit.
Set “F0
16
” in the I
2
C status register (address 00F8
16
) to generate
a START condition. At this time, an SCL for 1 byte and an ACK
clock automatically occurs.
Set transmit data in the I
2
C data shift register (address 00F6
16
).
At this time, an SCL and an ACK clock automatically occurs.
When transmitting control data of more than 1 byte, repeat step
.
Set “D0
16
” in the I
2
C status register (address 00F8
16
). After this,
if ACK is not returned or transmission ends, a STOP condition will
be generated.
(12) Example of Slave Reception
An example of slave reception in the high-speed clock mode, at the
SCL frequency of 400 kHz, in the ACK non-return mode, using the
addressing format, is shown below.
Set a slave address in the high-order 7 bits of the I
2
C address
register (address 00F7
16
) and “0” in the RBW bit.
Set the no ACK clock mode and SCL = 400 kHz by setting “25
16
in the I
2
C clock control register (address 00FA
16
).
Set “10
16
” in the I
2
C status register (address 00F8
16
) and hold
the SCL at the HIGH.
Set a communication enable status by setting “48
16
” in the I
2
C
control register (address 00F9
16
).
When a START condition is received, an address comparison is
made.
When all transmitted addresses are “0” (general call) :
AD0 of the I
2
C status register (address 00F8
16
) is set to “1” and
an interrupt request signal occurs.
When the transmitted addresses match the address set in
:
AAS of the I
2
C status register (address 00F8
16
) is set to “1” and
an interrupt request signal occurs.
In the cases other than the above :
AD0 and AAS of the I
2
C status register (address 00F8
16
) are
set to “0” and no interrupt request signal occurs.
Set dummy data in the I
2
C data shift register (address 00F6
16
).
When receiving control data of more than 1 byte, repeat step
.
When a STOP condition is detected, the communication ends.
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