參數(shù)資料
型號： M37274MA
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 8 Bits Microcomputer(8位單片機(jī))
中文描述： 單芯片8位單片機(jī)（8位單片機(jī)）
文件頁數(shù)： 15/131頁
文件大小： 2049K
代理商： M37274MA
15
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274MA-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
Fig. 8. Memory Map of Special Function Register 2 (SFR2) (2)
230
16
231
16
232
16
233
16
234
16
235
16
236
16
237
16
238
16
239
16
23A
16
23B
16
23C
16
23D
16
23E
16
23F
16
240
16
241
16
242
16
243
16
244
16
245
16
246
16
247
16
248
16
220
16
221
16
222
16
223
16
224
16
225
16
226
16
227
16
228
16
229
16
22A
16
22B
16
22C
16
22D
16
22E
16
22F
16
Vertical position register 1
11
(VP1
11
)
Vertical position register 1
12
(VP1
12
)
Vertical position register 1
3
(VP1
3
)
Vertical position register 1
4
(VP1
4
)
Vertical position register 1
7
(VP1
7
)
Vertical position register 1
8
(VP1
8
)
Vertical position register 1
5
(VP1
5
)
Vertical position register 1
6
(VP1
6
)
Vertical position register 1
1
(VP1
1
)
Vertical position register 1
2
(VP1
2
)
Vertical position register 1
9
(VP1
9
)
Vertical position register 1
10
(VP1
10
)
b7
b0 b7
b0
VP1
1
1
Vertical position register 2
3
(VP2
3
)
Vertical position register 2
4
(VP2
4
)
Vertical position register 2
7
(VP2
7
)
Vertical position register 2
8
(VP2
8
)
Vertical position register 2
5
(VP2
5
)
Vertical position register 2
6
(VP2
6
)
Vertical position register 2
1
(VP2
1
)
Vertical position register 2
2
(VP2
2
)
Vertical position register 2
9
(VP2
9
)
Vertical position register 2
10
(VP2
10
)
Vertical position register 2
11
(VP2
11
)
Vertical position register 2
12
(VP2
12
)
VP1
1
2
VP1
1
3
VP1
1
4
VP1
1
5
VP1
1
6
VP1
1
7
VP1
1
8
VP1
2
1
VP1
2
2
VP1
2
3
VP1
2
4
VP1
2
5
VP1
2
6
VP1
2
7
VP1
2
8
VP1
3
1
VP1
3
2
VP1
3
3
VP1
3
4
VP1
3
5
VP1
3
6
VP1
3
7
VP1
3
8
VP1
4
1
VP1
5
1
VP1
4
2
VP1
5
2
VP1
4
3
VP1
5
3
VP1
4
4
VP1
5
4
VP1
4
5
VP1
5
5
VP1
4
6
VP1
5
6
VP1
4
7
VP1
5
7
VP1
4
8
VP1
5
8
VP1
6
1
VP1
6
2
VP1
6
3
VP1
6
4
VP1
6
5
VP1
6
6
VP1
6
7
VP1
6
8
VP1
7
1
VP1
7
2
VP1
7
3
VP1
7
4
VP1
7
5
VP1
7
6
VP1
7
7
VP1
7
8
VP1
8
1
VP1
9
1
VP1
8
2
VP1
9
2
VP1
8
3
VP1
9
3
VP1
8
4
VP1
9
4
VP1
8
5
VP1
9
5
VP1
8
6
VP1
9
6
VP1
8
7
VP1
9
7
VP1
8
8
VP1
9
8
VP1
10
1
VP1
10
2
VP1
10
3
VP1
10
4
VP1
10
5
VP1
10
6
VP1
10
7
VP1
10
8
VP1
11
1
VP1
11
2
VP1
11
3
VP1
11
4
VP1
11
5
VP1
11
6
VP1
11
7
VP1
11
8
VP1
12
1
VP1
12
2
VP1
12
3
VP1
12
4
VP1
12
5
VP1
12
6
VP1
12
7
VP1
12
8
VP2
1
1
VP2
1
2
VP2
2
1
VP2
3
1
VP2
2
2
VP2
3
2
VP2
4
1
VP2
4
2
VP2
5
1
VP2
5
2
VP2
6
1
VP2
7
1
VP2
6
2
VP2
7
2
VP2
8
1
VP2
8
2
VP2
9
1
VP2
9
2
VP2
10
1
VP2
10
2
VP2
11
1
VP2
11
2
VP2
12
1
VP2
12
2
I
SFR2 area (addresses 220
16
to 248
16
)
Address
Register
Bit allocation
State immediately after reset
: Fix to this bit to “0”
(do not write to “1”)
:
<
Bit allocation
>
State immediately after reset
Function bit
:
No function bit
: Fix to this bit to “1”
(do not write to “0”)
Name
:
: “0” immediately after reset
: Indeterminate immediately
after reset
0
1
: “1” immediately after reset
1
0
ROM correction address 1 (high-order)
ROM correction address 1 (low-order)
ROM correction enable register (RCR)
ROM correction address 2 (high-order)
ROM correction address 2 (low-order)
DA-H register
(DA-H)
DA-L register
(DA-L)
RCR0
RCR1
00
16
00
16
00
16
00
16
00
16
00
16
00
16
0
0
0
0
0
0
0
00
16
<
>
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