參數(shù)資料
型號(hào): M37274MA
廠商: Mitsubishi Electric Corporation
英文描述: Single Chip 8 Bits Microcomputer(8位單片機(jī))
中文描述: 單芯片8位單片機(jī)(8位單片機(jī))
文件頁(yè)數(shù): 35/131頁(yè)
文件大小: 2049K
代理商: M37274MA
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)當(dāng)前第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)
35
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274MA-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
(1) Clamping Circuit and Low-pass Filter
This filter attenuates the noise of the composite video signal input
from the CV
IN
pin. The CV
IN
pin to which composite video signal is
input requires a capacitor (0.1 μF) coupling outside. Pull down the
CV
IN
pin with a resistor of hundreds of kiloohms to 1 M . In addition,
we recommend to install externally a simple low-pass filter using a
resistor and a capacitor at the CV
IN
pin (refer to Figure 25).
(2) Sync Slice Circuit
This circuit takes out a composite sync signal from the output signal
of the low-pass filter. Figure 27 shows the structure of the sync slice
register.
(3) Synchronous Signal Separation Circuit
This circuit separates a horizontal synchronous signal and a vertical
synchronous signal from the composite sync signal taken out in the
sync slice circuit.
Horizontal synchronous signal (H
sep
)
A one-shot horizontal synchronous signal Hsep is generated at
the falling edge of the composite sync signal.
Vertical synchronous signal (V
sep
)
As a V
sep
signal generating method, it is possible to select one of
the following 2 methods by using bit 7 of the sync slice register
(address 00E3
16
).
Method 1
The “L” level width of the composite sync signal is
measured. If this width exceeds a certain time, a V
sep
signal is generated in synchronization with the rising
of the timing signal immediately after this “L” level.
Method 2
The “L” level width of the composite sync signal is
measured. If this width exceeds a certain time, it is
detected whether a falling of the composite sync
signal exits or not in the “L” level period of the timing
signal immediately after this “L” level. If a falling exists,
a V
sep
signal is generated in synchronization with
the rising of the timing signal (refer to Figure 28).
Figure 28 shows a V
sep
generating timing. The timing signal shown
in the figure is generated from the reference clock which the timing
generating circuit outputs.
Reading bit 5 of data slicer control register 2 permits determinating
the shape of the V-pulse portion of the composite sync signal. As
shown in Figure 29, when the A level matches the B level, this bit is
“0.” In the case of a mismatch, the bit is “1.”
For the pins RVCO and the HLF, connect a resistor and a capacitor
as shown in Figure 25. Make the length of wiring which is connected
to these pins as short as possible so that a leakage current may not
be generated.
Note:
It takes a few tens of milliseconds until the reference clock
becomes stable after the data slicer and the timing signal
generating circuit are started. In this period, various timing
signals, H
sep
signals and V
sep
signals become unstable. For
this reason, take stabilization time into consideration when
programming.
Fig. 27. Sync Slice Register
Fig. 28. Vsep Generating Timing (method 2)
0
0
0
0
7
Sync slice register
(SSL : address 00E3
16
)
Fix these bits to “0000101
2
Vertical synchronizing
signal (V
sep
) generating
method selection bit
0 : Method 1
1 : Method 2
0
0
1
1
Composite
sync signal
Timing
signal
V
sep
signal
A V
sep
signal is generated at a rising of the timing signal
immediately after the “L” level width of the composite
sync signal exceeds a certain time.
1
2
Measure “L” period
相關(guān)PDF資料
PDF描述
M374S1723ETS-C7A SDRAM Unbuffered Module
M366S3323ETS-C7A SDRAM Unbuffered Module
M366S3323ETU-C7A SDRAM Unbuffered Module
M374S1723ETU-C7A SDRAM Unbuffered Module
M374S3323ETS-C7A SDRAM Unbuffered Module
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M37274MA-052SP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
M37274MA-053SP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
M37274MA-082SP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
M37274MA-084SP 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER
M37274MA-XXXSP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER