參數(shù)資料
型號: M37274MA
廠商: Mitsubishi Electric Corporation
英文描述: Single Chip 8 Bits Microcomputer(8位單片機)
中文描述: 單芯片8位單片機(8位單片機)
文件頁數(shù): 48/131頁
文件大?。?/td> 2049K
代理商: M37274MA
48
MITSUBISHI MICROCOMPUTERS
M37274MA-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
(6) START Condition Generation Method
When the ESO bit of the I
2
C control register (address 00F9
16
) is “1,”
execute a write instruction to the I
2
C status register (address 00F8
16
)
to set the MST, TRX and BB bits to “1.” A START condition will then
be generated. After that, the bit counter becomes “000
2
” and an SCL
for 1 byte is output. The START condition generation timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 49 for the START condition gen-
eration timing diagram, and Table 9 for the START condition/STOP
condition generation timing table.
Fig. 49. START Condition Generation Timing Diagram
Fig. 48. Interrupt Request Signal Generation Timing
Fig. 47. I
2
C Status Register
(7) RESTART Condition Generation Method
To generate the RESTART condition, take the following sequence:
Set “20
16
” to the I
2
C status register (S1).
Write a transmit data to the I
2
C data shift register.
Set “F0
16
” to the I
2
C status register (S1) again.
<Example of Setting of RESTART Condition>
I
2
C status register
; S1 = 20
16
I
2
C data shift register ; S0 = transmit data after restart
I
2
C status register
; S1 = F0
16
7
MST
0
I
2
C status register
(S1 : address 00F8
16
)
Last receive bit (Note)
0 : Last bit = “0”
1 : Last bit = “1”
General call detecting flag
(Note)
0 : No general call detected
1 : General call detected
Slave address comparison flag
(Note)
0 : Address mismatch
1 : Address match
Arbitration lost detecting flag
(Note)
0 : Not detected
1 : Detected
I
2
C-BUS interface interrupt
request bit
0 : Interrupt request issued
1 : No interrupt request
issued
Bus busy flag
0 : Bus free
1 : Bus busy
Communication mode
specification bits
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
TRX BB PIN
AL AAS AD0 LRB
Note:
These bit and flags can be read out but cannot
be written.
SCL
PIN
IICIRQ
I
2
C status register
write signal
Set time for
BB flag
Hold time
Setup
time
SCL
SDA
BB flag
Setup
time
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