參數(shù)資料
型號： M37274MA
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 8 Bits Microcomputer(8位單片機)
中文描述： 單芯片8位單片機（8位單片機）
文件頁數(shù)： 46/131頁
文件大小： 2049K
代理商： M37274MA
46
MITSUBISHI MICROCOMPUTERS
M37274MA-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
Fig. 46. I
2
C Control Register
(5) I
2
C Status Register
The I
2
C status register (address 00F8
16
) controls the I
2
C-BUS inter-
face status. The low-order 4 bits are read-only bits and the high-
order 4 bits can be read out and written to.
I
Bit 0: Last Receive Bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an ACK
clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit
is set to “1.” Except in the ACK mode, the last bit value of received
data is input. The state of this bit is changed from “1” to “0” by execut-
ing a write instruction to the I
2
C data shift register (address 00F6
16
).
I
Bit 1: General Call Detecting Flag (AD0)
This bit is set to “1” when a general call
8
whose address data is all “0”
is received in the slave mode. By a general call of the master device,
every slave device receives control data after the general call. The
AD0 bit is set to “0” by detecting the STOP condition or START con-
dition.
8
General call: The master transmits the general call address “00
16
”
to all slaves.
I
Bit 2: Slave Address Comparison Flag (AAS)
This flag indicates a comparison result of address data.
In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions.
The address data immediately after occurrence of a START
condition matches the slave address stored in the high-order
7 bits of the I
2
C address register (address 00F7
16
).
A general call is received.
In the slave reception mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition.
When the address data is compared with the I
2
C address
register (8 bits consists of slave address and RBW), the first
bytes match.
The state of this bit is changed from “1” to “0” by executing a write
instruction to the I
2
C data shift register (address 00F6
16
).
Fig. 45. Connection Port Control by BSEL0 and BSEL1
“0”
“1” BSEL0
SCL1/P1
1
SCL2/P1
2
“0”
“1” BSEL1
“0”
“1” BSEL0
SDA1/P1
3
SDA2/P1
4
“0”
“1” BSEL1
Multi-master
I
2
C-BUS
interface
SCL
SDA
7
BSEL1 BSEL0SAD
ALS
ESO BC2
BC1
BC0
0
Connection control bits
between I
2
C-BUS
interface and ports
b7
b6
Connection port
0 0 : None
0 1 : SCL1, SDA1
1 0 : SCL2, SDA2
1 1 : SCL1, SDA1,
SCL2, SDA2
I
2
C control register
(S1D : address 00F9
16
)
Bit counter (Number of
transmit/receive bits)
b2 b1 b0
0 0 0 : 8
0 0 1 : 7
0 1 0 : 6
0 1 1 : 5
1 0 0 : 4
1 0 1 : 3
1 1 0 : 2
1 1 1 : 1
I
2
C-BUS interface use
enable bit
0 : Disabled
1 : Enabled
Data format selection bit
0 : Addressing format
1 : Free data format
Addressing format
selection bit
0 : 7-bit addressing
format
1 : 10-bit addressing
format
Note:
When using multi-master I
2
C-BUS interface, set bits 3 and
4 of the serial I/O mode register (address 0213
16
) to “1.”
Moreover, set the corresponding direction register to “1” to
use the port as multi-master I
2
C-BUS interface.
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