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40
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274MA-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
Fig. 36. Clock Run-in Register 1
Fig. 39. Clock Run-in Detect Registers 1 and 3
Fig. 38. Window Setting
Fig. 37. Clock Run-in Register 3
For the main data slice line, the count value of pulses in the window
is stored in clock run-in register 1 (address 00E6
16
; refer to Figure
36). For the sub-data slice line, the count value of pulses in the window
is stored in clock run-in register 3 (address 0209
16
; refer to Figure
37). When this count value is 4 to 6, it is determined as a clock run-in.
Accordingly, set the count value so that the window may start after
the first pulse of the clock run-in (refer to Figure 38).
The contents to be set in the window register are written at a falling
of the horizontal synchronous signal. For this reason, even if an
instruction for setting is executed, the contents of the register cannot
be rewritten until a falling of the horizontal synchronous signal.
For the main data slice line, reference clock is counted in the period
from a falling of the clock pulse set in bits 0 to 2 of clock run-in
detect register 2 (address 00E9
16
) to the next falling. The count value
is stored in bits 3 to 7 of clock run-in detect register 1 (address
00E8
16
) (When the count value exceeds “1F
16
,” “1F
16
” is held). For
the sub-data slice line, the count value is stored in bits 3 to 7 of
clock run-in detect register 3 (address 0208
16
). Read out these bits
after the occurence of a data slicer interrupt (refer to (11) Interrupt
Request Generating Circuit).
Figure 39 shows the structure of clock run-in detect registers 1 and
3.
7
0
Clock run-in count value of
main-data slice line
Clock run-in register 1
(CR1 : address 00E6
16
)
Fix these bits to “0101
2
”
0 1 0
1
7
Clock run-in count value of sub-data
slice line
Clock run-in register 3
(CR3 : address 0209
16
)
Data latch completion flag for caption data in
sub-data slice line
0: Data is not latched yet
1: Data is latched
i
Data slice line selection bit for interrupt
request
0: Main data slice line
1: Sub-data slice line
Interrupt mode selection bit
0: Interrupt occurs at end of data slice line
1: Interrupt occurs at completion of caption
data latch
a
8
When the count value
in the window is 4 to 6,
this is determined as a
clock run-in.
Horizontal
synchronous
signal
Composite
video signal
Window
Clock run-in
Start bit data +
16-bit data
Time to be set in the
window register
Time to be set in
the start bit position
register
7
0
Number of reference clocks to
be counted in one clock run-in
pulse period
Clock run-in detect registers 1, 3
( CRD1 : address 00E8
16
)
( CRD3 : address 0208
16
)
Test bits : read-only
0