17
EXTERNAL BUS INTERFACE
17-19
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
17.3 Read/Write Operations
(1) When the Bus Mode Control Register = "0"
External read/write operations are performed using the address bus, data bus and the signals CS0#–CS3#,
RD#, BHW#, BLW#, WAIT#, CLKOUT and BCLK. In the external read cycle, the RD# signal is "L" while
BHW# and BLW# both are "H," with data read in from only the necessary byte position. In the external write
cycle, the BHW# or BLW# signal output for the byte position to which to write is asserted "L" as data is
written to the bus.
When an external bus cycle starts, wait states are inserted as long as the WAIT# signal is "L," Unless
necessary, the WAIT# signal must always be held "H." If the WAIT function is unused, and P71MD in the P7
Operation Mode Register or P153MD in the P15 Operation Mode Register is cleared to “0”, the pin can be
used as port.
Figure 17.3.1 Internal Bus Access during Bus Free State
17.3 Read/Write Operations
Bus-free state
Internal bus access
"H"
CLKOUT
A9–A30
CS0#–CS3#
BHW#, BLW#
DB0–DB15
WAIT#
RD#
"H"
Hi-Z
Note 1: For details about the Bus Mode Control Register, see Section 17.2.2, "Bus Mode Control Register."
Note: Hi-Z denotes a high-impedance state.
(Don't Care)
Bus Mode Control Register (Note 1)
BUSMOD bit = 0 (WR signal separated)