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10-176
10.8 TOU (Output-Related 24-Bit Timer)
MULTIJUNCTION TIMERS
10
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
(2) Reload register updates in TOU PWM output mode
In PWM output mode, when the timer remains idle, the reload 0 and reload 1 registers are updated at the
same time data are written to the respective registers. While the timer is operating, the reload 1 register is
updated when reload 0 register is reloaded after updating the reload 0 register. However, if the reload 0 and
reload 1 registers are accessed for read, the read values are always the data that have been written to the
respective registers.
TOUnRL1
F/F
TO
TOUnRL0
Internal bus
Reload 1
Reload 1 WR
Reload 0 WR
Reload 1 Buffer
16-bit counter
Prescaler output
Reload 0
PWM mode control
(Note 1)
Note 1: It is transferd from reload 1 register to reload 1 buffer when reload 0 register is reloaded
after updating reload 0 register during counter operation.
Figure 10.8.8 PWM Circuit Diagram
To rewrite the reload 0 and reload 1 registers while the timer is operating, rewrite the reload 1 register first
and then the reload 0 register. That way, the reload 0 and reload 1 registers both are updated synchro-
nously with PWM period, from which the timer starts operating. This operation can normally be performed
collectively by accessing 32-bit addresses beginning with the reload 1 register address wordwise. (Data are
automatically written to the reload 1 and then the reload 0 registers in succession.)
If the reload 0 and reload 1 registers are accessed for read, the read values are always the data that have
been written to the respective registers, and not the reload values being actually used.
When altering PWM period by rewriting the reload registers, if the PWM period terminates before the CPU
finishes writing to reload 0 register, the PWM period is not altered in the current session and the data written
to the register is reflected in the next period.
When operating in the PWM output mode, writing the reload 0 register and reloard 1 register more than
twice within the PWM period and meet the following conditions at the same time, the PWM waveform is
output with the value that the last time written reload 0 register and finally written reload 1 register.
Condition 1: Start writing reload 0 register after latching the reload 0 register PWM period of the old PWM
output period.
Condition 2: Rewrite reload 1 register before latching PWM period of the new PWM output period and
start writing reload 0 register after latching PWM period.