
17
EXTERNAL BUS INTERFACE
17-18
32192/32195/32196 Group Hardware Manual
Rev.1.10 REJ09B0123-0110 Apr.06.07
17.2 External Bus Interface Related Registers
X8
1/4
PLL
1/2
CLKO
SEL
CLKOUT(external bus clock)
(32MHz-40MHz or 16MHz-20MHz)
XIN pin
(16MHz-20MHz)
BCLK (peripheral clock)
(32MHz-40MHz)
CPUCLK (CPU clock)
(128MHz-160MHz)
Figure 17.2.3 Block Diagram of the Clock Configuration
The output pins for the peripheral clock BCLK and the external bus clock BCLKOUT are listed in Table 17.2.1.
A CLKOUT and BCLK select structure is shown in Figure 17.2.4.
Table 17.2.1 Output Pins for CLKOUT and BCLK
PIN No.
Pin Name
Function
Set Value
78
P70/CLKOUT/WR#/BCLK
P70
P70MD=0
CLKOUT
P70MD=1, P70SMD=0, BUSMOD=0
WR#
P70MD=1, P70SMD=0, BUSMOD=1
BCLK
P70MD=1, P70SMD=1
133
P150/TIN0/CLKOUT/WR#
P150
P150MD=0
TIN0
P150MD=1, P150SMD=0
CLKOUT
P150MD=1, P150SMD=1, BUSMOD=0
WR#
P150MD=1, P150SMD=1, BUSMOD=1
Figure 17.2.4 A CLKOUT and BCLK Select Structure
SEL
PIN No. 133 output
P150
P150MD
SEL
TIN0
P150SMD
SEL
PIN No. 78 output
P70
P70MD
SEL
BCLK
P70SMD
SEL
CLKOUT
BUSMOD
WR#
Figure 17.2.3 shows the clock configuration of CPUCLK, BCLK and CLKOUT.