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參數(shù)資料
| 型號(hào)： | M32000D4BFP-80 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 32 Bits Microcomputer(32位 單片機(jī)) |
| 中文描述： | 32位單片微機(jī)（32位單片機(jī)） |
| 文件頁數(shù)： | 8/44頁 |
| 文件大小： | 448K |
| 代理商： | M32000D4BFP-80 |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
8
PIN DESCRIPTION (3/3)
type
bus
control
(cont.)
pin name
DC*
name
data complete
I/O
I/O
(Hi-Z)
function
When the M32000D4BFP-80 drives an external bus cycle, it
automatically inserts wait cycles until DC is input by the slave
device in the system bus.
When the M32000D4BFP-80 is in the hold state and the internal
DRAM is accessed from an external bus master,the
M32000D4BFP-80 outputs DC to notify to the external bus master
that the bus cycle to the internal DRAM has been completed.
Bus right request input pin of the system bus. When HREQ is an
"L" level, the M32000D4BFP-80 switches to the hold state.
Indicates that the M32000D4BFP-80 has switched to the hold
state and releases the bus right of the system bus to the requestor.
Signal input to the M32000D4BFP-80 when it is in the hold state
to request access to the internal DRAM from an external bus
master. When an "L"level is input to CS, the M32000D4
BFP-80 accesses the internal DRAM at the address input via
the address pins.
System break interrupt input pin. The SBI is not masked by the
IE bit in the PSW register. It is also used to return from CPU
sleep mode and to request the start of operation in slave mode.
External interrupt request input pin. It is also used to return from
CPU sleep mode and to request the start of operation the slave
mode.
Two programmable I/O ports.
______
hold
HACK
hold
acknowledge
chip
select
output
CS
input
interrupt
controller
SBI
system
break
interrupt
input
INT
external
interrupt
input
programm-
able I/O port
PP0, PP1
port
I/O
* This pin goes to high-impedance in the hold state.
The DC pin becomes an output pin when the CS signal is input to the M32000D4BFP-80.
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