參數(shù)資料
型號(hào)： M32000D4BFP-80
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 32 Bits Microcomputer(32位 單片機(jī))
中文描述： 32位單片微機(jī)（32位單片機(jī)）
文件頁(yè)數(shù)： 22/44頁(yè)
文件大?。?/td> 448K
代理商： M32000D4BFP-80
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
22
The M32000D4BFP-80 outputs the BURST signal and carries out a
burst transfer when reading "the word-size data aligned on the 32-bit
boundary" or "a maximum 4 words of instructions aligned on the 128-
bit boundary". The BURST signal is synchronized with the CLKIN
falling edge of the first bus access cycle and output "L" level. It re-
turns to an "H" level synchronized with the first CLKIN falling edge of
the last bus access cycle. Addresses A8 to A30 are output for each
cycle.
When burst reading 32-bit data, the MSB-side 16-bit read bus cycle
is carried out first followed by the LSB-side 16-bit read bus cycle.
When the cache memory operation mode is the instruction cache
mode, and burst reading of the instructions within the 128-bit bound-
ary for cache replacement occurs, the bus cycle is driven a fixed 8
times from an arbitrary 32-bit boundary address and to wraparound
within the 128-bit boundary. When other than the instruction cache
mode is selected and burst reading a set of instructions of less than
128 bits, consecutive bus cycles are driven from an arbitrary 32-bit
boundary address as the top to the 128-bit line (A28 to A30 = "111").
Fig. 20 4-word (128-bit) burst read timing (1-0-0-0-0-0-0-0 wait)
Fig. 19 1-word (32-bit) burst read timing (1-0 wait)
"H"
idle
CLKIN
BS
A8 - A30
SID, ST
BCH, BCL
BURST
D0 - D15
DC
R/W
burst read (1 word)
idle
"Hi-Z"
"Hi-Z"
Note:
"Hi-Z" means high-impedance, and indicates sampling timing.
Wait cycles can be inserted even when burst transferring by setting
DC = "H".
Wait cycles can be inserted even when burst transferring by setting DC = "H".
"H"
idle
CLKIN
BS
A8 - A30
SID, ST
BCH, BCL
BURST
D0 - D15
DC
R/W
burst read ( 4 words)
idle
"Hi-Z"
Note:
"Hi-Z" means high-impedance, and indicates sampling timing.
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