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參數(shù)資料
| 型號： | M32000D4BFP-80 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 32 Bits Microcomputer(32位 單片機(jī)) |
| 中文描述： | 32位單片微機(jī)（32位單片機(jī)） |
| 文件頁數(shù)： | 17/44頁 |
| 文件大?。?/td> | 448K |
| 代理商： | M32000D4BFP-80 |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
17
Internal memory system
The memory system built into the M32000D4BFP-80 has the follow-
ing characteristics.
internal 16M-bit (2M-byte) DRAM
internal 4K-byte cache memory
CPU, cache and internal DRAM are connected by a 128-bit bus
selectable cache memory operation mode
– internal instruction/data cache mode
– instruction cache mode
– cache-off mode
When the internal instruction/data cache mode is selected, the cache
memory functions as a cache for both instruction and data from the
internal DRAM, and caches all bus access to the DRAM. This mode
is for a system which uses the internal DRAM as main memory. Trans-
fer between the M32R CPU, cache memory and internal DRAM is
always carried out in blocks of 128 bits. Caching is carried out by the
direct map method. Writing is by the copy back method.
When the M32000D4BFP-80 access destination is an external space,
data transfer between the M32R CPU and the external device is car-
ried out via the bus interface unit (BIU). The BIU has a 128-bit data
buffer which converts the bus width between the 128-bit bus in the
M32000D4BFP-80 and the external bus. Caching is not applicable in
this case of data transfer.
When accessing the internal DRAM from an external bus master,
and a cache hit occurs (the accessed data is inside the cache), data
transfer between the cache memory and the external bus via the BIU
is carried out. When a cache miss occurs, (the accessed data is not
inside the cache) data transfer is carried out between the internal
DRAM and the external bus via the BIU without cache replacement.
cache control register (MCCR) < address: H'FFFF FFFF>
D24
D25
D26
D27
D28
D29
D30
D31
CP
CM0
CM1
<at reset: H'01>
R
0
D
24
bit name
CP
(cache purge)
Not assigned.
CM0, CM1
(cache mode)
function
0: no purge
1: purge
W
25 - 29
30, 31
0
00: cache mode
is not changed
01: cache-off mode
10: internal
instruction/data
cache mode
11: instruction cache
mode
R =
... read enabled
W =
: write disabled
R = 0 ... "0" when reading
W =
... write enabled
Fig. 12 Cache control register
Fig. 13 Internal instruction/data cache mode
128
external bus
(16 bits)
16
external bus
interface
M32000D4BFP-80
128
128
instruction/
data cache
DRAM
BIU
CPU
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