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參數(shù)資料
| 型號： | M32000D4BFP-80 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 32 Bits Microcomputer(32位 單片機) |
| 中文描述： | 32位單片微機（32位單片機） |
| 文件頁數(shù)： | 18/44頁 |
| 文件大?。?/td> | 448K |
| 代理商： | M32000D4BFP-80 |
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SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
M32000D4BFP-80
18
When the instruction cache mode is selected, the cache functions as
an instruction cache for the internal DRAM or the external memory,
and caching is carried out for instruction fetch access. This mode is
designed for use when an external ROM is used as program memory
and the internal DRAM is used as data memory, or when instructions
are located in the internal DRAM. Caching is carried out by the direct
map method. When instruction codes in the user space are overwrit-
ten by the external bus master or another source, instruction code
coherency in the cache memory is not guaranteed. Furthermore,
caching is not applied when accessing the internal DRAM from the
external bus master.
When the cache-off mode is selected, the M32000D4BFP-80 inter-
nal memory system is configured as follows. In this mode, caching is
not applied, and all bus cycles are directly to the internal DRAM or
external bus.
Fig. 14 Instruction cache mode
Fig. 15 Cache-off mode
external bus
(16 bits)
16
einterface
M32000D4BFP-80
128
AAAA
AAAA
cache
BIU
128
DRAM
CPU
AAAAA
AAAAA
AAAAA
AAAAA
128
external bus
(16 bits)
16
M32000D4BFP-80
128
DRAM
BIU
CPU
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